Lines Matching refs:port
96 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
100 static void yukon_init(struct skge_hw *hw, int port);
101 static void genesis_mac_init(struct skge_hw *hw, int port);
164 int port = skge->port;
168 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
183 skge_write32(hw, SK_REG(port, GPHY_CTRL),
188 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
196 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
200 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
201 gm_phy_write(hw, port, PHY_MARV_CTRL,
207 gma_write16(hw, port, GM_GP_CTRL,
212 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
216 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
229 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
232 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
303 cmd->base.port = PORT_TP;
306 cmd->base.port = PORT_FIBRE;
622 int port = skge->port;
631 if (msk & rxirqmask[port])
633 if (msk & txirqmask[port])
640 /* Note: interrupt timer is per board, but can turn on/off per port */
646 int port = skge->port;
651 msk &= ~rxirqmask[port];
656 msk |= rxirqmask[port];
661 msk &= ~txirqmask[port];
666 msk |= txirqmask[port];
684 int port = skge->port;
691 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
693 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
694 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
696 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
697 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
698 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
703 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
705 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
706 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
711 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
712 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
713 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
716 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
718 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
719 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
720 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
727 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
728 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
736 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
742 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
748 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
749 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
1052 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1067 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
1074 static void xm_link_down(struct skge_hw *hw, int port)
1076 struct net_device *dev = hw->dev[port];
1079 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1085 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1089 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1090 *val = xm_read16(hw, port, XM_PHY_DATA);
1096 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1103 *val = xm_read16(hw, port, XM_PHY_DATA);
1108 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1111 if (__xm_phy_read(hw, port, reg, &v))
1112 pr_warn("%s: phy read timed out\n", hw->dev[port]->name);
1116 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1120 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1122 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1129 xm_write16(hw, port, XM_PHY_DATA, val);
1131 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1166 static void genesis_reset(struct skge_hw *hw, int port)
1171 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1174 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1175 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1176 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1177 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1178 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1182 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1184 xm_outhash(hw, port, XM_HSM, zero);
1187 reg = xm_read32(hw, port, XM_MODE);
1188 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1189 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1210 static void bcom_check_link(struct skge_hw *hw, int port)
1212 struct net_device *dev = hw->dev[port];
1217 xm_phy_read(hw, port, PHY_BCOM_STAT);
1218 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1221 xm_link_down(hw, port);
1231 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1237 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1279 int port = skge->port;
1298 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1301 r = xm_read16(hw, port, XM_MMU_CMD);
1303 xm_write16(hw, port, XM_MMU_CMD, r);
1312 xm_phy_write(hw, port,
1322 xm_phy_write(hw, port,
1331 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1333 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1336 xm_read16(hw, port, XM_ISRC);
1352 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1359 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1363 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1367 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1368 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1375 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1376 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1379 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1385 int port = skge->port;
1396 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1410 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1420 int port = skge->port;
1424 xm_phy_read(hw, port, PHY_XMAC_STAT);
1425 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1428 xm_link_down(hw, port);
1438 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1444 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1494 int port = skge->port;
1508 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1514 u16 msk = xm_read16(hw, port, XM_IMSK);
1516 xm_write16(hw, port, XM_IMSK, msk);
1517 xm_read16(hw, port, XM_ISRC);
1526 static void genesis_mac_init(struct skge_hw *hw, int port)
1528 struct net_device *dev = hw->dev[port];
1530 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1536 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1538 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1547 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1557 if (port == 0)
1565 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1575 bcom_check_link(hw, port);
1579 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1583 xm_outaddr(hw, port, XM_EXM(i), zero);
1586 xm_write16(hw, port, XM_STAT_CMD,
1589 xm_write16(hw, port, XM_STAT_CMD,
1593 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1608 xm_write16(hw, port, XM_RX_CMD, r);
1611 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1613 /* Increase threshold for jumbo frames on dual port */
1615 xm_write16(hw, port, XM_TX_THR, 1020);
1617 xm_write16(hw, port, XM_TX_THR, 512);
1633 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1641 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1648 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1665 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1666 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1667 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1670 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1671 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1672 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1676 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1680 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1687 int port = skge->port;
1692 cmd = xm_read16(hw, port, XM_MMU_CMD);
1694 xm_write16(hw, port, XM_MMU_CMD, cmd);
1696 genesis_reset(hw, port);
1700 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1703 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1705 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1706 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1713 if (port == 0) {
1724 xm_write16(hw, port, XM_MMU_CMD,
1725 xm_read16(hw, port, XM_MMU_CMD)
1728 xm_read16(hw, port, XM_MMU_CMD);
1735 int port = skge->port;
1739 xm_write16(hw, port,
1743 while (xm_read16(hw, port, XM_STAT_CMD)
1751 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1752 | xm_read32(hw, port, XM_TXO_OK_LO);
1753 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1754 | xm_read32(hw, port, XM_RXO_OK_LO);
1757 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1760 static void genesis_mac_intr(struct skge_hw *hw, int port)
1762 struct net_device *dev = hw->dev[port];
1764 u16 status = xm_read16(hw, port, XM_ISRC);
1770 xm_link_down(hw, port);
1775 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1783 int port = skge->port;
1787 cmd = xm_read16(hw, port, XM_MMU_CMD);
1801 xm_write16(hw, port, XM_MMU_CMD, cmd);
1803 mode = xm_read32(hw, port, XM_MODE);
1817 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1820 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1829 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1832 xm_write32(hw, port, XM_MODE, mode);
1835 msk = xm_read16(hw, port, XM_IMSK);
1837 xm_write16(hw, port, XM_IMSK, msk);
1839 xm_read16(hw, port, XM_ISRC);
1842 cmd = xm_read16(hw, port, XM_MMU_CMD);
1851 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1852 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1854 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1858 xm_write16(hw, port, XM_MMU_CMD,
1867 int port = skge->port;
1870 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1876 hw->dev[port]->name);
1882 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1883 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1885 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1890 bcom_check_link(hw, port);
1894 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1898 gma_write16(hw, port, GM_SMI_DATA, val);
1899 gma_write16(hw, port, GM_SMI_CTRL,
1904 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1908 pr_warn("%s: phy write timeout\n", hw->dev[port]->name);
1912 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1916 gma_write16(hw, port, GM_SMI_CTRL,
1922 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1928 *val = gma_read16(hw, port, GM_SMI_DATA);
1932 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1935 if (__gm_phy_read(hw, port, reg, &v))
1936 pr_warn("%s: phy read timeout\n", hw->dev[port]->name);
1941 static void yukon_init(struct skge_hw *hw, int port)
1943 struct skge_port *skge = netdev_priv(hw->dev[port]);
1947 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1955 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1958 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1963 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2016 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2018 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2019 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2023 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2025 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2028 static void yukon_reset(struct skge_hw *hw, int port)
2030 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2031 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2032 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2033 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2034 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2036 gma_write16(hw, port, GM_RX_CTRL,
2037 gma_read16(hw, port, GM_RX_CTRL)
2057 static void yukon_mac_init(struct skge_hw *hw, int port)
2059 struct skge_port *skge = netdev_priv(hw->dev[port]);
2062 const u8 *addr = hw->dev[port]->dev_addr;
2073 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2074 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2091 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2092 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2093 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2097 gma_write16(hw, port, GM_GP_CTRL,
2098 gma_read16(hw, port, GM_GP_CTRL) | reg);
2121 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2134 gma_write16(hw, port, GM_GP_CTRL, reg);
2135 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2137 yukon_init(hw, port);
2140 reg = gma_read16(hw, port, GM_PHY_ADDR);
2141 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2144 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2145 gma_write16(hw, port, GM_PHY_ADDR, reg);
2148 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2151 gma_write16(hw, port, GM_RX_CTRL,
2155 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2158 gma_write16(hw, port, GM_TX_PARAM,
2168 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2171 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2174 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2176 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2179 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2180 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2181 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2186 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2193 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2194 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2200 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2203 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2204 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2208 static void yukon_suspend(struct skge_hw *hw, int port)
2212 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2214 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2216 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2218 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2221 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2223 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2229 int port = skge->port;
2231 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2232 yukon_reset(hw, port);
2234 gma_write16(hw, port, GM_GP_CTRL,
2235 gma_read16(hw, port, GM_GP_CTRL)
2237 gma_read16(hw, port, GM_GP_CTRL);
2239 yukon_suspend(hw, port);
2242 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2243 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2249 int port = skge->port;
2252 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2253 | gma_read32(hw, port, GM_TXO_OK_LO);
2254 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2255 | gma_read32(hw, port, GM_RXO_OK_LO);
2258 data[i] = gma_read32(hw, port,
2262 static void yukon_mac_intr(struct skge_hw *hw, int port)
2264 struct net_device *dev = hw->dev[port];
2266 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2273 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2278 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2298 int port = skge->port;
2302 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2304 reg = gma_read16(hw, port, GM_GP_CTRL);
2310 gma_write16(hw, port, GM_GP_CTRL, reg);
2312 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2319 int port = skge->port;
2322 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2324 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2327 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2330 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2335 yukon_init(hw, port);
2341 int port = skge->port;
2345 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2346 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2352 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2358 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2389 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2391 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2417 int port = skge->port;
2418 struct net_device *dev = hw->dev[port];
2425 genesis_reset(hw, port);
2426 genesis_mac_init(hw, port);
2428 yukon_reset(hw, port);
2429 yukon_init(hw, port);
2457 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2459 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2468 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2471 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2531 int port = skge->port;
2590 genesis_mac_init(hw, port);
2592 yukon_mac_init(hw, port);
2597 ram_addr = hw->ram_offset + 2 * chunk * port;
2599 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2600 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2603 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2604 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2608 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2612 hw->intr_mask |= portmask[port];
2637 static void skge_rx_stop(struct skge_hw *hw, int port)
2639 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2640 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2642 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2649 int port = skge->port;
2665 hw->intr_mask &= ~portmask[port];
2673 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
2680 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2681 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2686 skge_write8(hw, SK_REG(port, TXA_CTRL),
2690 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2691 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2694 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2695 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2698 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2700 skge_rx_stop(hw, port);
2703 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2704 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2706 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2707 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2818 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2891 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2931 int port = skge->port;
2936 mode = xm_read32(hw, port, XM_MODE);
2956 xm_write32(hw, port, XM_MODE, mode);
2957 xm_outhash(hw, port, XM_HSM, filter);
2970 int port = skge->port;
2979 reg = gma_read16(hw, port, GM_RX_CTRL);
2999 gma_write16(hw, port, GM_MC_ADDR_H1,
3001 gma_write16(hw, port, GM_MC_ADDR_H2,
3003 gma_write16(hw, port, GM_MC_ADDR_H3,
3005 gma_write16(hw, port, GM_MC_ADDR_H4,
3008 gma_write16(hw, port, GM_RX_CTRL, reg);
3150 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3200 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3222 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3228 hw->intr_mask |= napimask[skge->port];
3240 static void skge_mac_parity(struct skge_hw *hw, int port)
3242 struct net_device *dev = hw->dev[port];
3247 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3251 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3256 static void skge_mac_intr(struct skge_hw *hw, int port)
3259 genesis_mac_intr(hw, port);
3261 yukon_mac_intr(hw, port);
3344 int port;
3346 for (port = 0; port < hw->ports; port++) {
3347 struct net_device *dev = hw->dev[port];
3450 unsigned port = skge->port;
3460 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3461 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3465 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3466 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3468 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3469 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3472 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3474 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3475 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3478 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3511 * the port(s)
3667 /* Leave irq disabled until first port is brought up. */
3803 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3846 hw->dev[port] = dev;
3848 skge->port = port;
3860 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);