Lines Matching defs:port
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
61 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port))
67 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
68 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
69 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
70 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
71 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
72 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
73 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
74 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
100 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
114 #define MVPP2_CLS_FLOW_TBL0_PORT_ID(port) ((port) << 4)
128 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
131 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
133 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
143 #define MVPP22_CLS_C2_PORT_ID(port) ((port) << 8)
255 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port))
260 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port))
275 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
278 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
289 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
346 /* Packet Processor per-port counters */
352 #define MVPP22_CTRS_TX_CTR(port, txq) ((txq) | ((port) << 3) | BIT(7))
397 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
407 /* Per-port registers */
472 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
473 * relative to port->base.
577 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00)
586 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)
597 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
604 #define MVPP22_PTP_BASE(port) (0x7800 + (port * 0x1000))
692 /* Maximum number of T-CONTs of PON port */
698 /* Maximum number of TXQs used by single port */
708 /* Max number of RXQs per port */
956 /* On PPv2.2, some port control registers are located into the system
968 /* List of pointers to port structures */
998 /* Maximum number of RXQs per port */
1034 /* Per-CPU port control */
1050 struct mvpp2_port *port;
1093 /* Index of the port from the "group of ports" complex point
1102 /* Firmware node associated to the port */
1105 /* Is a PHY always connected to the port */
1108 /* Per-port registers' base address */
1122 /* Per-CPU port control */
1141 /* Per-port work and its lock to gather hardware statistics */
1156 /* Index of first port's physical RXQ */
1165 /* List of steering rules active on that port */
1169 /* Each port has its own view of the rss contexts, so that it can number
1387 /* ID of port to which physical RXQ is mapped */
1388 int port;
1467 static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port)
1469 return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;