Lines Matching defs:mvreg_write
722 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
824 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
830 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
856 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
876 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
900 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
916 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
934 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
973 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
984 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
995 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1008 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1021 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1040 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
1066 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1067 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1070 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1072 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
1075 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
1079 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
1082 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1207 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1224 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1234 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1248 mvreg_write(pp, MVNETA_RXQ_CMD,
1271 mvreg_write(pp, MVNETA_TXQ_CMD,
1316 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1327 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1348 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1365 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1385 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1395 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1408 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1409 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1410 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1420 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1421 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1422 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1446 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1449 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1481 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1485 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1486 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1489 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1491 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1492 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1495 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1496 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1505 mvreg_write(pp, MVNETA_ACC_MODE, val);
1508 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1512 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1515 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1516 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1531 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1538 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1545 mvreg_write(pp, MVNETA_INTR_ENABLE,
1567 mvreg_write(pp, MVNETA_TX_MTU, val);
1577 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1587 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1619 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1634 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1635 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1648 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1664 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1678 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1703 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1708 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
2948 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2981 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
3041 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
3042 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
3049 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
3050 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
3095 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
3144 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
3182 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
3280 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
3281 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
3286 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
3287 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
3313 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
3314 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
3428 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
3429 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
3432 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
3433 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
3482 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
3483 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
3486 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
3487 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
3578 mvreg_write(pp, MVNETA_SERDES_CFG,
3584 mvreg_write(pp, MVNETA_SERDES_CFG,
3589 mvreg_write(pp, MVNETA_SERDES_CFG,
3629 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3899 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3901 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3979 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3998 mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
4000 mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
4002 mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
4004 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
4006 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
4024 mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
4040 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4077 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4089 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4173 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
4240 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4281 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4777 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
4896 mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
5002 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
5003 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
5006 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
5016 mvreg_write(pp, MVNETA_WIN_BASE(i),
5021 mvreg_write(pp, MVNETA_WIN_SIZE(i),
5032 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
5037 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
5038 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
5045 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);