Lines Matching defs:mvreg_read
728 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
757 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
758 mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
759 mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
840 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
896 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
911 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
968 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
982 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
993 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1004 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1017 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1038 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
1050 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
1077 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
1244 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1262 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1268 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1286 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1301 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1314 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1325 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1536 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1564 val = mvreg_read(pp, MVNETA_TX_MTU);
1570 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1580 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1609 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1673 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1718 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
2938 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2971 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
3032 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
3034 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
3114 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3140 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
3142 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
3780 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3781 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3871 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3897 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3910 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
3911 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3912 u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
3913 u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
3914 u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4009 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
4019 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
4037 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4058 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4083 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4170 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
4872 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4893 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);