Lines Matching defs:jme
32 #include "jme.h"
49 struct jme_adapter *jme = netdev_priv(netdev);
53 jwrite32(jme, JME_SMI, SMI_OP_REQ |
60 val = jread32(jme, JME_SMI);
80 struct jme_adapter *jme = netdev_priv(netdev);
83 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
90 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
99 jme_reset_phy_processor(struct jme_adapter *jme)
103 jme_mdio_write(jme->dev,
104 jme->mii_if.phy_id,
108 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
109 jme_mdio_write(jme->dev,
110 jme->mii_if.phy_id,
114 val = jme_mdio_read(jme->dev,
115 jme->mii_if.phy_id,
118 jme_mdio_write(jme->dev,
119 jme->mii_if.phy_id,
124 jme_setup_wakeup_frame(struct jme_adapter *jme,
132 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
134 jwrite32(jme, JME_WFODP, crc);
141 jwrite32(jme, JME_WFOI,
145 jwrite32(jme, JME_WFODP, mask[i]);
151 jme_mac_rxclk_off(struct jme_adapter *jme)
153 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
154 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
158 jme_mac_rxclk_on(struct jme_adapter *jme)
160 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
161 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
165 jme_mac_txclk_off(struct jme_adapter *jme)
167 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
168 jwrite32f(jme, JME_GHC, jme->reg_ghc);
172 jme_mac_txclk_on(struct jme_adapter *jme)
174 u32 speed = jme->reg_ghc & GHC_SPEED;
176 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
178 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
179 jwrite32f(jme, JME_GHC, jme->reg_ghc);
183 jme_reset_ghc_speed(struct jme_adapter *jme)
185 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
186 jwrite32f(jme, JME_GHC, jme->reg_ghc);
190 jme_reset_250A2_workaround(struct jme_adapter *jme)
192 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
194 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
198 jme_assert_ghc_reset(struct jme_adapter *jme)
200 jme->reg_ghc |= GHC_SWRST;
201 jwrite32f(jme, JME_GHC, jme->reg_ghc);
205 jme_clear_ghc_reset(struct jme_adapter *jme)
207 jme->reg_ghc &= ~GHC_SWRST;
208 jwrite32f(jme, JME_GHC, jme->reg_ghc);
212 jme_reset_mac_processor(struct jme_adapter *jme)
219 jme_reset_ghc_speed(jme);
220 jme_reset_250A2_workaround(jme);
222 jme_mac_rxclk_on(jme);
223 jme_mac_txclk_on(jme);
225 jme_assert_ghc_reset(jme);
227 jme_mac_rxclk_off(jme);
228 jme_mac_txclk_off(jme);
230 jme_clear_ghc_reset(jme);
232 jme_mac_rxclk_on(jme);
233 jme_mac_txclk_on(jme);
235 jme_mac_rxclk_off(jme);
236 jme_mac_txclk_off(jme);
238 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
239 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
240 jwrite32(jme, JME_RXQDC, 0x00000000);
241 jwrite32(jme, JME_RXNDA, 0x00000000);
242 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
243 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
244 jwrite32(jme, JME_TXQDC, 0x00000000);
245 jwrite32(jme, JME_TXNDA, 0x00000000);
247 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
248 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
250 jme_setup_wakeup_frame(jme, mask, crc, i);
251 if (jme->fpgaver)
255 jwrite32(jme, JME_GPREG0, gpreg0);
259 jme_clear_pm_enable_wol(struct jme_adapter *jme)
261 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
265 jme_clear_pm_disable_wol(struct jme_adapter *jme)
267 jwrite32(jme, JME_PMCS, PMCS_STMASK);
271 jme_reload_eeprom(struct jme_adapter *jme)
276 val = jread32(jme, JME_SMBCSR);
280 jwrite32(jme, JME_SMBCSR, val);
282 jwrite32(jme, JME_SMBCSR, val);
287 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
303 struct jme_adapter *jme = netdev_priv(netdev);
307 spin_lock_bh(&jme->macaddr_lock);
308 val = jread32(jme, JME_RXUMA_LO);
313 val = jread32(jme, JME_RXUMA_HI);
317 spin_unlock_bh(&jme->macaddr_lock);
321 jme_set_rx_pcc(struct jme_adapter *jme, int p)
325 jwrite32(jme, JME_PCCRX0,
330 jwrite32(jme, JME_PCCRX0,
335 jwrite32(jme, JME_PCCRX0,
340 jwrite32(jme, JME_PCCRX0,
349 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
350 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
354 jme_start_irq(struct jme_adapter *jme)
356 register struct dynpcc_info *dpi = &(jme->dpi);
358 jme_set_rx_pcc(jme, PCC_P1);
363 jwrite32(jme, JME_PCCTX,
372 jwrite32(jme, JME_IENS, INTR_ENABLE);
376 jme_stop_irq(struct jme_adapter *jme)
381 jwrite32f(jme, JME_IENC, INTR_ENABLE);
385 jme_linkstat_from_phy(struct jme_adapter *jme)
389 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
390 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
398 jme_set_phyfifo_5level(struct jme_adapter *jme)
400 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
404 jme_set_phyfifo_8level(struct jme_adapter *jme)
406 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
412 struct jme_adapter *jme = netdev_priv(netdev);
419 if (jme->fpgaver)
420 phylink = jme_linkstat_from_phy(jme);
422 phylink = jread32(jme, JME_PHY_LINK);
432 bmcr = jme_mdio_read(jme->dev,
433 jme->mii_if.phy_id,
456 if (jme->fpgaver)
457 phylink = jme_linkstat_from_phy(jme);
459 phylink = jread32(jme, JME_PHY_LINK);
467 if (jme->phylink == phylink) {
474 jme->phylink = phylink;
477 * The speed/duplex setting of jme->reg_ghc already cleared
482 jme->reg_ghc |= GHC_SPEED_10M;
486 jme->reg_ghc |= GHC_SPEED_100M;
490 jme->reg_ghc |= GHC_SPEED_1000M;
498 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
499 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
500 jme->reg_ghc |= GHC_DPX;
502 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
506 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
509 jwrite32(jme, JME_GHC, jme->reg_ghc);
511 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
512 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
515 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
518 jme_set_phyfifo_8level(jme);
519 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
522 jme_set_phyfifo_5level(jme);
523 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
526 jme_set_phyfifo_8level(jme);
532 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
540 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
546 netif_info(jme, link, jme->dev, "Link is down\n");
547 jme->phylink = 0;
556 jme_setup_tx_resources(struct jme_adapter *jme)
558 struct jme_ring *txring = &(jme->txring[0]);
560 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
561 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
576 atomic_set(&txring->nr_free, jme->tx_ring_size);
578 txring->bufinf = kcalloc(jme->tx_ring_size,
587 dma_free_coherent(&(jme->pdev->dev),
588 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
602 jme_free_tx_resources(struct jme_adapter *jme)
605 struct jme_ring *txring = &(jme->txring[0]);
610 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
624 dma_free_coherent(&(jme->pdev->dev),
625 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
641 jme_enable_tx_engine(struct jme_adapter *jme)
646 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
652 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
653 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
654 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
659 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
665 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
672 jme_mac_txclk_on(jme);
676 jme_disable_tx_engine(struct jme_adapter *jme)
684 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
687 val = jread32(jme, JME_TXCS);
690 val = jread32(jme, JME_TXCS);
700 jme_mac_txclk_off(jme);
704 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
706 struct jme_ring *rxring = &(jme->rxring[0]);
718 if (jme->dev->features & NETIF_F_HIGHDMA)
725 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
727 struct jme_ring *rxring = &(jme->rxring[0]);
732 skb = netdev_alloc_skb(jme->dev,
733 jme->dev->mtu + RX_EXTRA_LEN);
737 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
740 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
746 pci_unmap_page(jme->pdev, rxbi->mapping,
756 jme_free_rx_buf(struct jme_adapter *jme, int i)
758 struct jme_ring *rxring = &(jme->rxring[0]);
763 pci_unmap_page(jme->pdev,
775 jme_free_rx_resources(struct jme_adapter *jme)
778 struct jme_ring *rxring = &(jme->rxring[0]);
782 for (i = 0 ; i < jme->rx_ring_size ; ++i)
783 jme_free_rx_buf(jme, i);
787 dma_free_coherent(&(jme->pdev->dev),
788 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
802 jme_setup_rx_resources(struct jme_adapter *jme)
805 struct jme_ring *rxring = &(jme->rxring[0]);
807 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
808 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
823 rxring->bufinf = kcalloc(jme->rx_ring_size,
832 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
833 if (unlikely(jme_make_new_rx_buf(jme, i))) {
834 jme_free_rx_resources(jme);
838 jme_set_clean_rxdesc(jme, i);
844 dma_free_coherent(&(jme->pdev->dev),
845 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
858 jme_enable_rx_engine(struct jme_adapter *jme)
863 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
870 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
871 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
872 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
877 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
882 jme_set_unicastaddr(jme->dev);
883 jme_set_multi(jme->dev);
889 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
897 jme_mac_rxclk_on(jme);
901 jme_restart_rx_engine(struct jme_adapter *jme)
906 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
913 jme_disable_rx_engine(struct jme_adapter *jme)
921 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
924 val = jread32(jme, JME_RXCS);
927 val = jread32(jme, JME_RXCS);
937 jme_mac_rxclk_off(jme);
967 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
975 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
982 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
988 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
996 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
998 struct jme_ring *rxring = &(jme->rxring[0]);
1008 pci_dma_sync_single_for_cpu(jme->pdev,
1013 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1014 pci_dma_sync_single_for_device(jme->pdev,
1019 ++(NET_STAT(jme).rx_dropped);
1026 skb->protocol = eth_type_trans(skb, jme->dev);
1028 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1037 NET_STAT(jme).rx_bytes += 4;
1039 jme->jme_rx(skb);
1043 ++(NET_STAT(jme).multicast);
1045 NET_STAT(jme).rx_bytes += framesize;
1046 ++(NET_STAT(jme).rx_packets);
1049 jme_set_clean_rxdesc(jme, idx);
1054 jme_process_receive(struct jme_adapter *jme, int limit)
1056 struct jme_ring *rxring = &(jme->rxring[0]);
1058 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1060 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1063 if (unlikely(atomic_read(&jme->link_changing) != 1))
1066 if (unlikely(!netif_carrier_ok(jme->dev)))
1086 ++(NET_STAT(jme).rx_crc_errors);
1088 ++(NET_STAT(jme).rx_fifo_errors);
1090 ++(NET_STAT(jme).rx_errors);
1096 jme_set_clean_rxdesc(jme, j);
1101 jme_alloc_and_feed_skb(jme, i);
1111 atomic_inc(&jme->rx_cleaning);
1135 jme_dynamic_pcc(struct jme_adapter *jme)
1137 register struct dynpcc_info *dpi = &(jme->dpi);
1139 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1141 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1149 tasklet_schedule(&jme->rxclean_task);
1150 jme_set_rx_pcc(jme, dpi->attempt);
1157 jme_start_pcc_timer(struct jme_adapter *jme)
1159 struct dynpcc_info *dpi = &(jme->dpi);
1160 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1161 dpi->last_pkts = NET_STAT(jme).rx_packets;
1163 jwrite32(jme, JME_TMCSR,
1168 jme_stop_pcc_timer(struct jme_adapter *jme)
1170 jwrite32(jme, JME_TMCSR, 0);
1174 jme_shutdown_nic(struct jme_adapter *jme)
1178 phylink = jme_linkstat_from_phy(jme);
1184 jme_stop_irq(jme);
1185 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1192 struct jme_adapter *jme = from_tasklet(jme, t, pcc_task);
1193 struct net_device *netdev = jme->dev;
1195 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1196 jme_shutdown_nic(jme);
1201 (atomic_read(&jme->link_changing) != 1)
1203 jme_stop_pcc_timer(jme);
1207 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1208 jme_dynamic_pcc(jme);
1210 jme_start_pcc_timer(jme);
1214 jme_polling_mode(struct jme_adapter *jme)
1216 jme_set_rx_pcc(jme, PCC_OFF);
1220 jme_interrupt_mode(struct jme_adapter *jme)
1222 jme_set_rx_pcc(jme, PCC_P1);
1226 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1229 apmc = jread32(jme, JME_APMC);
1234 jme_start_shutdown_timer(struct jme_adapter *jme)
1238 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1241 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1244 jwrite32f(jme, JME_APMC, apmc);
1246 jwrite32f(jme, JME_TIMER2, 0);
1247 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1248 jwrite32(jme, JME_TMCSR,
1253 jme_stop_shutdown_timer(struct jme_adapter *jme)
1257 jwrite32f(jme, JME_TMCSR, 0);
1258 jwrite32f(jme, JME_TIMER2, 0);
1259 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1261 apmc = jread32(jme, JME_APMC);
1263 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1265 jwrite32f(jme, JME_APMC, apmc);
1270 struct jme_adapter *jme = from_tasklet(jme, t, linkch_task);
1271 struct net_device *netdev = jme->dev;
1274 while (!atomic_dec_and_test(&jme->link_changing)) {
1275 atomic_inc(&jme->link_changing);
1276 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1277 while (atomic_read(&jme->link_changing) != 1)
1278 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1281 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1284 jme->old_mtu = netdev->mtu;
1286 if (jme_pseudo_hotplug_enabled(jme))
1287 jme_stop_shutdown_timer(jme);
1289 jme_stop_pcc_timer(jme);
1290 tasklet_disable(&jme->txclean_task);
1291 tasklet_disable(&jme->rxclean_task);
1292 tasklet_disable(&jme->rxempty_task);
1295 jme_disable_rx_engine(jme);
1296 jme_disable_tx_engine(jme);
1297 jme_reset_mac_processor(jme);
1298 jme_free_rx_resources(jme);
1299 jme_free_tx_resources(jme);
1301 if (test_bit(JME_FLAG_POLL, &jme->flags))
1302 jme_polling_mode(jme);
1309 rc = jme_setup_rx_resources(jme);
1315 rc = jme_setup_tx_resources(jme);
1321 jme_enable_rx_engine(jme);
1322 jme_enable_tx_engine(jme);
1326 if (test_bit(JME_FLAG_POLL, &jme->flags))
1327 jme_interrupt_mode(jme);
1329 jme_start_pcc_timer(jme);
1330 } else if (jme_pseudo_hotplug_enabled(jme)) {
1331 jme_start_shutdown_timer(jme);
1337 jme_free_rx_resources(jme);
1339 tasklet_enable(&jme->txclean_task);
1340 tasklet_enable(&jme->rxclean_task);
1341 tasklet_enable(&jme->rxempty_task);
1343 atomic_inc(&jme->link_changing);
1349 struct jme_adapter *jme = from_tasklet(jme, t, rxclean_task);
1350 struct dynpcc_info *dpi = &(jme->dpi);
1352 jme_process_receive(jme, jme->rx_ring_size);
1360 struct jme_adapter *jme = jme_napi_priv(holder);
1363 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1365 while (atomic_read(&jme->rx_empty) > 0) {
1366 atomic_dec(&jme->rx_empty);
1367 ++(NET_STAT(jme).rx_dropped);
1368 jme_restart_rx_engine(jme);
1370 atomic_inc(&jme->rx_empty);
1374 jme_interrupt_mode(jme);
1384 struct jme_adapter *jme = from_tasklet(jme, t, rxempty_task);
1386 if (unlikely(atomic_read(&jme->link_changing) != 1))
1389 if (unlikely(!netif_carrier_ok(jme->dev)))
1392 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1394 jme_rx_clean_tasklet(&jme->rxclean_task);
1396 while (atomic_read(&jme->rx_empty) > 0) {
1397 atomic_dec(&jme->rx_empty);
1398 ++(NET_STAT(jme).rx_dropped);
1399 jme_restart_rx_engine(jme);
1401 atomic_inc(&jme->rx_empty);
1405 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1407 struct jme_ring *txring = &(jme->txring[0]);
1410 if (unlikely(netif_queue_stopped(jme->dev) &&
1411 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1412 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1413 netif_wake_queue(jme->dev);
1420 struct jme_adapter *jme = from_tasklet(jme, t, txclean_task);
1421 struct jme_ring *txring = &(jme->txring[0]);
1426 tx_dbg(jme, "Into txclean\n");
1428 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1431 if (unlikely(atomic_read(&jme->link_changing) != 1))
1434 if (unlikely(!netif_carrier_ok(jme->dev)))
1437 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1438 mask = jme->tx_ring_mask;
1447 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1456 pci_unmap_page(jme->pdev,
1470 ++(NET_STAT(jme).tx_carrier_errors);
1472 ++(NET_STAT(jme).tx_packets);
1473 NET_STAT(jme).tx_bytes += ctxbi->len;
1489 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1493 jme_wake_queue_if_stopped(jme);
1496 atomic_inc(&jme->tx_cleaning);
1500 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1505 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1512 jwrite32(jme, JME_IEVE, intrstat);
1513 tasklet_schedule(&jme->linkch_task);
1518 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1519 tasklet_schedule(&jme->pcc_task);
1523 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1524 tasklet_schedule(&jme->txclean_task);
1528 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1534 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1536 atomic_inc(&jme->rx_empty);
1539 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1540 jme_polling_mode(jme);
1541 JME_RX_SCHEDULE(jme);
1546 atomic_inc(&jme->rx_empty);
1547 tasklet_hi_schedule(&jme->rxempty_task);
1549 tasklet_hi_schedule(&jme->rxclean_task);
1557 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1564 struct jme_adapter *jme = netdev_priv(netdev);
1567 intrstat = jread32(jme, JME_IEVE);
1581 jme_intr_msi(jme, intrstat);
1590 struct jme_adapter *jme = netdev_priv(netdev);
1593 intrstat = jread32(jme, JME_IEVE);
1595 jme_intr_msi(jme, intrstat);
1601 jme_reset_link(struct jme_adapter *jme)
1603 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1607 jme_restart_an(struct jme_adapter *jme)
1611 spin_lock_bh(&jme->phy_lock);
1612 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1614 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1615 spin_unlock_bh(&jme->phy_lock);
1619 jme_request_irq(struct jme_adapter *jme)
1622 struct net_device *netdev = jme->dev;
1626 if (!pci_enable_msi(jme->pdev)) {
1627 set_bit(JME_FLAG_MSI, &jme->flags);
1632 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1637 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1640 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1641 pci_disable_msi(jme->pdev);
1642 clear_bit(JME_FLAG_MSI, &jme->flags);
1645 netdev->irq = jme->pdev->irq;
1652 jme_free_irq(struct jme_adapter *jme)
1654 free_irq(jme->pdev->irq, jme->dev);
1655 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1656 pci_disable_msi(jme->pdev);
1657 clear_bit(JME_FLAG_MSI, &jme->flags);
1658 jme->dev->irq = jme->pdev->irq;
1663 jme_new_phy_on(struct jme_adapter *jme)
1667 reg = jread32(jme, JME_PHY_PWR);
1670 jwrite32(jme, JME_PHY_PWR, reg);
1672 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1675 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1679 jme_new_phy_off(struct jme_adapter *jme)
1683 reg = jread32(jme, JME_PHY_PWR);
1686 jwrite32(jme, JME_PHY_PWR, reg);
1688 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1691 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1695 jme_phy_on(struct jme_adapter *jme)
1699 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1701 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1703 if (new_phy_power_ctrl(jme->chip_main_rev))
1704 jme_new_phy_on(jme);
1708 jme_phy_off(struct jme_adapter *jme)
1712 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1714 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1716 if (new_phy_power_ctrl(jme->chip_main_rev))
1717 jme_new_phy_off(jme);
1721 jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1726 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1728 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1733 jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1738 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1740 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1745 jme_phy_calibration(struct jme_adapter *jme)
1749 jme_phy_off(jme);
1750 jme_phy_on(jme);
1752 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1755 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1757 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1761 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1763 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1767 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1770 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1772 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1777 jme_phy_setEA(struct jme_adapter *jme)
1782 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1786 switch (jme->pdev->device) {
1788 if (((jme->chip_main_rev == 5) &&
1789 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1790 (jme->chip_sub_rev == 3))) ||
1791 (jme->chip_main_rev >= 6)) {
1795 if ((jme->chip_main_rev == 3) &&
1796 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1800 if (((jme->chip_main_rev == 5) &&
1801 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1802 (jme->chip_sub_rev == 3))) ||
1803 (jme->chip_main_rev >= 6)) {
1807 if ((jme->chip_main_rev == 3) &&
1808 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1810 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1812 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1819 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1821 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1829 struct jme_adapter *jme = netdev_priv(netdev);
1832 jme_clear_pm_disable_wol(jme);
1833 JME_NAPI_ENABLE(jme);
1835 tasklet_setup(&jme->linkch_task, jme_link_change_tasklet);
1836 tasklet_setup(&jme->txclean_task, jme_tx_clean_tasklet);
1837 tasklet_setup(&jme->rxclean_task, jme_rx_clean_tasklet);
1838 tasklet_setup(&jme->rxempty_task, jme_rx_empty_tasklet);
1840 rc = jme_request_irq(jme);
1844 jme_start_irq(jme);
1846 jme_phy_on(jme);
1847 if (test_bit(JME_FLAG_SSET, &jme->flags))
1848 jme_set_link_ksettings(netdev, &jme->old_cmd);
1850 jme_reset_phy_processor(jme);
1851 jme_phy_calibration(jme);
1852 jme_phy_setEA(jme);
1853 jme_reset_link(jme);
1864 jme_set_100m_half(struct jme_adapter *jme)
1868 jme_phy_on(jme);
1869 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1875 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1877 if (jme->fpgaver)
1878 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1880 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1885 jme_wait_link(struct jme_adapter *jme)
1890 phylink = jme_linkstat_from_phy(jme);
1893 phylink = jme_linkstat_from_phy(jme);
1898 jme_powersave_phy(struct jme_adapter *jme)
1900 if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) {
1901 jme_set_100m_half(jme);
1902 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1903 jme_wait_link(jme);
1904 jme_clear_pm_enable_wol(jme);
1906 jme_phy_off(jme);
1913 struct jme_adapter *jme = netdev_priv(netdev);
1918 jme_stop_irq(jme);
1919 jme_free_irq(jme);
1921 JME_NAPI_DISABLE(jme);
1923 tasklet_kill(&jme->linkch_task);
1924 tasklet_kill(&jme->txclean_task);
1925 tasklet_kill(&jme->rxclean_task);
1926 tasklet_kill(&jme->rxempty_task);
1928 jme_disable_rx_engine(jme);
1929 jme_disable_tx_engine(jme);
1930 jme_reset_mac_processor(jme);
1931 jme_free_rx_resources(jme);
1932 jme_free_tx_resources(jme);
1933 jme->phylink = 0;
1934 jme_phy_off(jme);
1940 jme_alloc_txdesc(struct jme_adapter *jme,
1943 struct jme_ring *txring = &(jme->txring[0]);
1944 int idx, nr_alloc, mask = jme->tx_ring_mask;
1998 static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count)
2000 struct jme_ring *txring = &(jme->txring[0]);
2002 int mask = jme->tx_ring_mask;
2007 pci_unmap_page(jme->pdev,
2018 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2020 struct jme_ring *txring = &(jme->txring[0]);
2023 bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
2025 int mask = jme->tx_ring_mask;
2035 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2039 jme_drop_tx_map(jme, idx, i);
2047 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2050 jme_drop_tx_map(jme, idx, i);
2084 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2109 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2125 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2127 struct jme_ring *txring = &(jme->txring[0]);
2154 jme_tx_csum(jme, skb, &flags);
2156 ret = jme_map_tx_skb(jme, skb, idx);
2177 jme_stop_queue_if_full(struct jme_adapter *jme)
2179 struct jme_ring *txring = &(jme->txring[0]);
2187 netif_stop_queue(jme->dev);
2188 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2191 >= (jme->tx_wake_threshold)) {
2192 netif_wake_queue(jme->dev);
2193 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2200 netif_stop_queue(jme->dev);
2201 netif_info(jme, tx_queued, jme->dev,
2213 struct jme_adapter *jme = netdev_priv(netdev);
2218 ++(NET_STAT(jme).tx_dropped);
2222 idx = jme_alloc_txdesc(jme, skb);
2226 netif_err(jme, tx_err, jme->dev,
2232 if (jme_fill_tx_desc(jme, skb, idx))
2235 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2240 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2242 jme_stop_queue_if_full(jme);
2250 struct jme_adapter *jme = netdev_priv(netdev);
2257 jwrite32(jme, JME_RXUMA_LO, val);
2260 jwrite32(jme, JME_RXUMA_HI, val);
2266 struct jme_adapter *jme = netdev_priv(netdev);
2272 spin_lock_bh(&jme->macaddr_lock);
2275 spin_unlock_bh(&jme->macaddr_lock);
2283 struct jme_adapter *jme = netdev_priv(netdev);
2286 spin_lock_bh(&jme->rxmcs_lock);
2288 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2291 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2293 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2298 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2304 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2305 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2309 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2311 spin_unlock_bh(&jme->rxmcs_lock);
2317 struct jme_adapter *jme = netdev_priv(netdev);
2322 jme_restart_rx_engine(jme);
2323 jme_reset_link(jme);
2331 struct jme_adapter *jme = netdev_priv(netdev);
2333 jme->phylink = 0;
2334 jme_reset_phy_processor(jme);
2335 if (test_bit(JME_FLAG_SSET, &jme->flags))
2336 jme_set_link_ksettings(netdev, &jme->old_cmd);
2341 jme_reset_link(jme);
2348 struct jme_adapter *jme = netdev_priv(netdev);
2352 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
2362 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2367 p[i >> 2] = jread32(jme, reg + i);
2371 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2377 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2383 struct jme_adapter *jme = netdev_priv(netdev);
2389 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2392 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2395 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2398 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2401 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2407 struct jme_adapter *jme = netdev_priv(netdev);
2412 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2421 switch (jme->dpi.cur) {
2444 struct jme_adapter *jme = netdev_priv(netdev);
2445 struct dynpcc_info *dpi = &(jme->dpi);
2451 test_bit(JME_FLAG_POLL, &jme->flags)) {
2452 clear_bit(JME_FLAG_POLL, &jme->flags);
2453 jme->jme_rx = netif_rx;
2457 jme_set_rx_pcc(jme, PCC_P1);
2458 jme_interrupt_mode(jme);
2460 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2461 set_bit(JME_FLAG_POLL, &jme->flags);
2462 jme->jme_rx = netif_receive_skb;
2463 jme_interrupt_mode(jme);
2473 struct jme_adapter *jme = netdev_priv(netdev);
2476 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2477 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2479 spin_lock_bh(&jme->phy_lock);
2480 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2481 spin_unlock_bh(&jme->phy_lock);
2491 struct jme_adapter *jme = netdev_priv(netdev);
2494 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2498 jme->reg_txpfc |= TXPFC_PF_EN;
2500 jme->reg_txpfc &= ~TXPFC_PF_EN;
2502 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2505 spin_lock_bh(&jme->rxmcs_lock);
2506 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2510 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2512 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2514 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2516 spin_unlock_bh(&jme->rxmcs_lock);
2518 spin_lock_bh(&jme->phy_lock);
2519 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2528 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2531 spin_unlock_bh(&jme->phy_lock);
2540 struct jme_adapter *jme = netdev_priv(netdev);
2546 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2549 if (jme->reg_pmcs & PMCS_MFEN)
2558 struct jme_adapter *jme = netdev_priv(netdev);
2567 jme->reg_pmcs = 0;
2570 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2573 jme->reg_pmcs |= PMCS_MFEN;
2582 struct jme_adapter *jme = netdev_priv(netdev);
2584 spin_lock_bh(&jme->phy_lock);
2585 mii_ethtool_get_link_ksettings(&jme->mii_if, cmd);
2586 spin_unlock_bh(&jme->phy_lock);
2594 struct jme_adapter *jme = netdev_priv(netdev);
2605 if (jme->mii_if.force_media &&
2607 (jme->mii_if.full_duplex != cmd->base.duplex))
2610 spin_lock_bh(&jme->phy_lock);
2611 rc = mii_ethtool_set_link_ksettings(&jme->mii_if, cmd);
2612 spin_unlock_bh(&jme->phy_lock);
2616 jme_reset_link(jme);
2617 jme->old_cmd = *cmd;
2618 set_bit(JME_FLAG_SSET, &jme->flags);
2628 struct jme_adapter *jme = netdev_priv(netdev);
2639 spin_lock_bh(&jme->phy_lock);
2640 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2641 spin_unlock_bh(&jme->phy_lock);
2645 jme_reset_link(jme);
2646 jme_get_link_ksettings(netdev, &jme->old_cmd);
2647 set_bit(JME_FLAG_SSET, &jme->flags);
2656 struct jme_adapter *jme = netdev_priv(netdev);
2657 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2663 struct jme_adapter *jme = netdev_priv(netdev);
2664 return jme->msg_enable;
2670 struct jme_adapter *jme = netdev_priv(netdev);
2671 jme->msg_enable = value;
2685 struct jme_adapter *jme = netdev_priv(netdev);
2687 spin_lock_bh(&jme->rxmcs_lock);
2689 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2691 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2692 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2693 spin_unlock_bh(&jme->rxmcs_lock);
2712 struct jme_adapter *jme = netdev_priv(netdev);
2713 jme_restart_an(jme);
2718 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2723 val = jread32(jme, JME_SMBCSR);
2727 val = jread32(jme, JME_SMBCSR);
2730 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2734 jwrite32(jme, JME_SMBINTF,
2739 val = jread32(jme, JME_SMBINTF);
2743 val = jread32(jme, JME_SMBINTF);
2746 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2754 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2759 val = jread32(jme, JME_SMBCSR);
2763 val = jread32(jme, JME_SMBCSR);
2766 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2770 jwrite32(jme, JME_SMBINTF,
2776 val = jread32(jme, JME_SMBINTF);
2780 val = jread32(jme, JME_SMBINTF);
2783 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2793 struct jme_adapter *jme = netdev_priv(netdev);
2795 val = jread32(jme, JME_SMBCSR);
2803 struct jme_adapter *jme = netdev_priv(netdev);
2811 data[i] = jme_smb_read(jme, i + offset);
2820 struct jme_adapter *jme = netdev_priv(netdev);
2830 jme_smb_write(jme, i + offset, data[i]);
2880 jme_phy_init(struct jme_adapter *jme)
2884 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2885 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2889 jme_check_hw_ver(struct jme_adapter *jme)
2893 chipmode = jread32(jme, JME_CHIPMODE);
2895 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2896 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2897 jme->chip_main_rev = jme->chiprev & 0xF;
2898 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2924 struct jme_adapter *jme;
2964 netdev = alloc_etherdev(sizeof(*jme));
2998 jme = netdev_priv(netdev);
2999 jme->pdev = pdev;
3000 jme->dev = netdev;
3001 jme->jme_rx = netif_rx;
3002 jme->old_mtu = netdev->mtu = 1500;
3003 jme->phylink = 0;
3004 jme->tx_ring_size = 1 << 10;
3005 jme->tx_ring_mask = jme->tx_ring_size - 1;
3006 jme->tx_wake_threshold = 1 << 9;
3007 jme->rx_ring_size = 1 << 9;
3008 jme->rx_ring_mask = jme->rx_ring_size - 1;
3009 jme->msg_enable = JME_DEF_MSG_ENABLE;
3010 jme->regs = ioremap(pci_resource_start(pdev, 0),
3012 if (!(jme->regs)) {
3019 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3020 jwrite32(jme, JME_APMC, apmc);
3022 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3023 jwrite32(jme, JME_APMC, apmc);
3026 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, NAPI_POLL_WEIGHT)
3028 spin_lock_init(&jme->phy_lock);
3029 spin_lock_init(&jme->macaddr_lock);
3030 spin_lock_init(&jme->rxmcs_lock);
3032 atomic_set(&jme->link_changing, 1);
3033 atomic_set(&jme->rx_cleaning, 1);
3034 atomic_set(&jme->tx_cleaning, 1);
3035 atomic_set(&jme->rx_empty, 1);
3037 tasklet_setup(&jme->pcc_task, jme_pcc_tasklet);
3038 jme->dpi.cur = PCC_P1;
3040 jme->reg_ghc = 0;
3041 jme->reg_rxcs = RXCS_DEFAULT;
3042 jme->reg_rxmcs = RXMCS_DEFAULT;
3043 jme->reg_txpfc = 0;
3044 jme->reg_pmcs = PMCS_MFEN;
3045 jme->reg_gpreg1 = GPREG1_DEFAULT;
3047 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3053 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3054 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3055 switch (jme->mrrs) {
3057 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3060 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3063 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3070 jme_check_hw_ver(jme);
3071 jme->mii_if.dev = netdev;
3072 if (jme->fpgaver) {
3073 jme->mii_if.phy_id = 0;
3078 jme->mii_if.phy_id = i;
3083 if (!jme->mii_if.phy_id) {
3089 jme->reg_ghc |= GHC_LINK_POLL;
3091 jme->mii_if.phy_id = 1;
3094 jme->mii_if.supports_gmii = true;
3096 jme->mii_if.supports_gmii = false;
3097 jme->mii_if.phy_id_mask = 0x1F;
3098 jme->mii_if.reg_num_mask = 0x1F;
3099 jme->mii_if.mdio_read = jme_mdio_read;
3100 jme->mii_if.mdio_write = jme_mdio_write;
3102 jme_clear_pm_disable_wol(jme);
3105 jme_set_phyfifo_5level(jme);
3106 jme->pcirev = pdev->revision;
3107 if (!jme->fpgaver)
3108 jme_phy_init(jme);
3109 jme_phy_off(jme);
3114 jme_reset_mac_processor(jme);
3115 rc = jme_reload_eeprom(jme);
3133 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3134 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3136 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3138 (jme->fpgaver != 0) ? " (FPGA)" : "",
3139 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3140 jme->pcirev, netdev->dev_addr);
3145 iounmap(jme->regs);
3160 struct jme_adapter *jme = netdev_priv(netdev);
3163 iounmap(jme->regs);
3174 struct jme_adapter *jme = netdev_priv(netdev);
3176 jme_powersave_phy(jme);
3185 struct jme_adapter *jme = netdev_priv(netdev);
3190 atomic_dec(&jme->link_changing);
3194 jme_stop_irq(jme);
3196 tasklet_disable(&jme->txclean_task);
3197 tasklet_disable(&jme->rxclean_task);
3198 tasklet_disable(&jme->rxempty_task);
3201 if (test_bit(JME_FLAG_POLL, &jme->flags))
3202 jme_polling_mode(jme);
3204 jme_stop_pcc_timer(jme);
3205 jme_disable_rx_engine(jme);
3206 jme_disable_tx_engine(jme);
3207 jme_reset_mac_processor(jme);
3208 jme_free_rx_resources(jme);
3209 jme_free_tx_resources(jme);
3211 jme->phylink = 0;
3214 tasklet_enable(&jme->txclean_task);
3215 tasklet_enable(&jme->rxclean_task);
3216 tasklet_enable(&jme->rxempty_task);
3218 jme_powersave_phy(jme);
3227 struct jme_adapter *jme = netdev_priv(netdev);
3232 jme_clear_pm_disable_wol(jme);
3233 jme_phy_on(jme);
3234 if (test_bit(JME_FLAG_SSET, &jme->flags))
3235 jme_set_link_ksettings(netdev, &jme->old_cmd);
3237 jme_reset_phy_processor(jme);
3238 jme_phy_calibration(jme);
3239 jme_phy_setEA(jme);
3242 atomic_inc(&jme->link_changing);
3244 jme_reset_link(jme);
3246 jme_start_irq(jme);