Lines Matching defs:address
615 /* Set the base address for flash register access */
626 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
749 * @address: EMI address to program
750 * @data: pointer to value to read/write from/to the EMI address
755 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
760 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
775 * @addr: EMI address to program
776 * @data: value to be read from the EMI address
788 * @addr: EMI address to program
789 * @data: value to be written to the EMI address
1858 * e1000_rar_set_pch2lan - Set receive address register
1860 * @addr: pointer to the receive address
1861 * @index: receive address array register
1863 * Sets the receive address array register at index to the address passed
1864 * in by addr. For 82579, RAR[0] is the base address register that is to
1865 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1881 /* If MAC address zero, no need to set the AV bit */
1894 * next address into the SHRA register array.
1920 e_dbg("Failed to write receive address at index %d\n", index);
1929 * program. SHRA[0-10] are the shared receive address registers
1961 * e1000_rar_set_pch_lpt - Set receive address registers
1963 * @addr: pointer to the receive address
1964 * @index: receive address array register
1966 * Sets the receive address register array at index to the address passed
1967 * in by addr. For LPT, RAR[0] is the base address register that is to
1968 * contain the MAC address. SHRA[0-10] are the shared receive address
1984 /* If MAC address zero, no need to set the AV bit */
2030 e_dbg("Failed to write receive address at index %d\n", index);
2054 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2167 /* HW configures the SMBus address and LEDs when the
4507 /* Start with the base address, then add the sector offset. */
4537 * block into Flash Linear address field in Flash
4806 * - setup receive address registers
4826 /* Setup the receive address. */