Lines Matching defs:mal
3 * drivers/net/ethernet/ibm/emac/mal.c
32 int mal_register_commac(struct mal_instance *mal, struct mal_commac *commac)
36 spin_lock_irqsave(&mal->lock, flags);
38 MAL_DBG(mal, "reg(%08x, %08x)" NL,
42 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
43 (mal->rx_chan_mask & commac->rx_chan_mask)) {
44 spin_unlock_irqrestore(&mal->lock, flags);
45 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
46 mal->index);
50 if (list_empty(&mal->list))
51 napi_enable(&mal->napi);
52 mal->tx_chan_mask |= commac->tx_chan_mask;
53 mal->rx_chan_mask |= commac->rx_chan_mask;
54 list_add(&commac->list, &mal->list);
56 spin_unlock_irqrestore(&mal->lock, flags);
61 void mal_unregister_commac(struct mal_instance *mal,
66 spin_lock_irqsave(&mal->lock, flags);
68 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
71 mal->tx_chan_mask &= ~commac->tx_chan_mask;
72 mal->rx_chan_mask &= ~commac->rx_chan_mask;
74 if (list_empty(&mal->list))
75 napi_disable(&mal->napi);
77 spin_unlock_irqrestore(&mal->lock, flags);
80 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
82 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
85 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
89 "mal%d: incorrect RX size %lu for the channel %d\n",
90 mal->index, size, channel);
94 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
98 int mal_tx_bd_offset(struct mal_instance *mal, int channel)
100 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
105 int mal_rx_bd_offset(struct mal_instance *mal, int channel)
107 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
108 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
111 void mal_enable_tx_channel(struct mal_instance *mal, int channel)
115 spin_lock_irqsave(&mal->lock, flags);
117 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
119 set_mal_dcrn(mal, MAL_TXCASR,
120 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
122 spin_unlock_irqrestore(&mal->lock, flags);
125 void mal_disable_tx_channel(struct mal_instance *mal, int channel)
127 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
129 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
132 void mal_enable_rx_channel(struct mal_instance *mal, int channel)
144 spin_lock_irqsave(&mal->lock, flags);
146 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
148 set_mal_dcrn(mal, MAL_RXCASR,
149 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
151 spin_unlock_irqrestore(&mal->lock, flags);
154 void mal_disable_rx_channel(struct mal_instance *mal, int channel)
164 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
166 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
169 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
173 spin_lock_irqsave(&mal->lock, flags);
175 MAL_DBG(mal, "poll_add(%p)" NL, commac);
180 list_add_tail(&commac->poll_list, &mal->poll_list);
182 spin_unlock_irqrestore(&mal->lock, flags);
185 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
189 spin_lock_irqsave(&mal->lock, flags);
191 MAL_DBG(mal, "poll_del(%p)" NL, commac);
195 spin_unlock_irqrestore(&mal->lock, flags);
199 static inline void mal_enable_eob_irq(struct mal_instance *mal)
201 MAL_DBG2(mal, "enable_irq" NL);
204 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
208 static inline void mal_disable_eob_irq(struct mal_instance *mal)
211 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
213 MAL_DBG2(mal, "disable_irq" NL);
218 struct mal_instance *mal = dev_instance;
220 u32 esr = get_mal_dcrn(mal, MAL_ESR);
223 set_mal_dcrn(mal, MAL_ESR, esr);
225 MAL_DBG(mal, "SERR %08x" NL, esr);
241 "mal%d: system error, "
243 mal->index, esr);
252 "mal%d: system error, OPB (ESR = 0x%08x)\n",
253 mal->index, esr);
258 static inline void mal_schedule_poll(struct mal_instance *mal)
260 if (likely(napi_schedule_prep(&mal->napi))) {
261 MAL_DBG2(mal, "schedule_poll" NL);
262 spin_lock(&mal->lock);
263 mal_disable_eob_irq(mal);
264 spin_unlock(&mal->lock);
265 __napi_schedule(&mal->napi);
267 MAL_DBG2(mal, "already in poll" NL);
272 struct mal_instance *mal = dev_instance;
274 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
276 MAL_DBG2(mal, "txeob %08x" NL, r);
278 mal_schedule_poll(mal);
279 set_mal_dcrn(mal, MAL_TXEOBISR, r);
282 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
292 struct mal_instance *mal = dev_instance;
294 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
296 MAL_DBG2(mal, "rxeob %08x" NL, r);
298 mal_schedule_poll(mal);
299 set_mal_dcrn(mal, MAL_RXEOBISR, r);
302 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
312 struct mal_instance *mal = dev_instance;
314 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
315 set_mal_dcrn(mal, MAL_TXDEIR, deir);
317 MAL_DBG(mal, "txde %08x" NL, deir);
321 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
322 mal->index, deir);
329 struct mal_instance *mal = dev_instance;
332 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
334 MAL_DBG(mal, "rxde %08x" NL, deir);
336 list_for_each(l, &mal->list) {
344 mal_schedule_poll(mal);
345 set_mal_dcrn(mal, MAL_RXDEIR, deir);
352 struct mal_instance *mal = dev_instance;
353 u32 esr = get_mal_dcrn(mal, MAL_ESR);
369 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
376 napi_synchronize(&mal->napi);
379 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
389 napi_schedule(&mal->napi);
394 struct mal_instance *mal = container_of(napi, struct mal_instance, napi);
399 MAL_DBG2(mal, "poll(%d)" NL, budget);
402 list_for_each(l, &mal->poll_list) {
413 list_for_each(l, &mal->poll_list) {
429 spin_lock_irqsave(&mal->lock, flags);
430 mal_enable_eob_irq(mal);
431 spin_unlock_irqrestore(&mal->lock, flags);
435 list_for_each(l, &mal->poll_list) {
442 MAL_DBG2(mal, "rotting packet" NL);
446 spin_lock_irqsave(&mal->lock, flags);
447 mal_disable_eob_irq(mal);
448 spin_unlock_irqrestore(&mal->lock, flags);
454 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received);
458 static void mal_reset(struct mal_instance *mal)
462 MAL_DBG(mal, "reset" NL);
464 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
467 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
471 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
474 int mal_get_regs_len(struct mal_instance *mal)
480 void *mal_dump_regs(struct mal_instance *mal, void *buf)
486 hdr->version = mal->version;
487 hdr->index = mal->index;
489 regs->tx_count = mal->num_tx_chans;
490 regs->rx_count = mal->num_rx_chans;
492 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
493 regs->esr = get_mal_dcrn(mal, MAL_ESR);
494 regs->ier = get_mal_dcrn(mal, MAL_IER);
495 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
496 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
497 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
498 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
499 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
500 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
501 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
502 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
505 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
508 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
509 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
516 struct mal_instance *mal;
525 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
526 if (!mal)
529 mal->index = index;
530 mal->ofdev = ofdev;
531 mal->version = of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal2") ? 2 : 1;
533 MAL_DBG(mal, "probe" NL);
538 "mal%d: can't find MAL num-tx-chans property!\n",
543 mal->num_tx_chans = prop[0];
548 "mal%d: can't find MAL num-rx-chans property!\n",
553 mal->num_rx_chans = prop[0];
558 "mal%d: can't find DCR resource!\n", index);
562 mal->dcr_host = dcr_map(ofdev->dev.of_node, dcr_base, 0x100);
563 if (!DCR_MAP_OK(mal->dcr_host)) {
565 "mal%d: failed to map DCRs !\n", index);
573 mal->features |= (MAL_FTR_CLEAR_ICINTSTAT |
583 mal->txeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
584 mal->rxeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
585 mal->serr_irq = irq_of_parse_and_map(ofdev->dev.of_node, 2);
587 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
588 mal->txde_irq = mal->rxde_irq = mal->serr_irq;
590 mal->txde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 3);
591 mal->rxde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 4);
594 if (!mal->txeob_irq || !mal->rxeob_irq || !mal->serr_irq ||
595 !mal->txde_irq || !mal->rxde_irq) {
597 "mal%d: failed to map interrupts !\n", index);
602 INIT_LIST_HEAD(&mal->poll_list);
603 INIT_LIST_HEAD(&mal->list);
604 spin_lock_init(&mal->lock);
606 init_dummy_netdev(&mal->dummy_dev);
608 netif_napi_add(&mal->dummy_dev, &mal->napi, mal_poll,
612 mal_reset(mal);
615 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
625 set_mal_dcrn(mal, MAL_CFG, cfg);
628 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
629 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
632 (NUM_TX_BUFF * mal->num_tx_chans +
633 NUM_RX_BUFF * mal->num_rx_chans);
634 mal->bd_virt = dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
636 if (mal->bd_virt == NULL) {
641 for (i = 0; i < mal->num_tx_chans; ++i)
642 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
644 mal_tx_bd_offset(mal, i));
646 for (i = 0; i < mal->num_rx_chans; ++i)
647 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
649 mal_rx_bd_offset(mal, i));
651 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
661 err = request_irq(mal->serr_irq, hdlr_serr, irqflags, "MAL SERR", mal);
664 err = request_irq(mal->txde_irq, hdlr_txde, irqflags, "MAL TX DE", mal);
667 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
670 err = request_irq(mal->rxde_irq, hdlr_rxde, irqflags, "MAL RX DE", mal);
673 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
678 set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS);
681 mal_enable_eob_irq(mal);
685 mal->version, ofdev->dev.of_node,
686 mal->num_tx_chans, mal->num_rx_chans);
690 platform_set_drvdata(ofdev, mal);
695 free_irq(mal->rxde_irq, mal);
697 free_irq(mal->txeob_irq, mal);
699 free_irq(mal->txde_irq, mal);
701 free_irq(mal->serr_irq, mal);
703 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
705 dcr_unmap(mal->dcr_host, 0x100);
707 kfree(mal);
714 struct mal_instance *mal = platform_get_drvdata(ofdev);
716 MAL_DBG(mal, "remove" NL);
719 napi_disable(&mal->napi);
721 if (!list_empty(&mal->list))
724 "mal%d: commac list is not empty on remove!\n",
725 mal->index);
727 free_irq(mal->serr_irq, mal);
728 free_irq(mal->txde_irq, mal);
729 free_irq(mal->txeob_irq, mal);
730 free_irq(mal->rxde_irq, mal);
731 free_irq(mal->rxeob_irq, mal);
733 mal_reset(mal);
737 (NUM_TX_BUFF * mal->num_tx_chans +
738 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
739 mal->bd_dma);
740 kfree(mal);