Lines Matching defs:val
128 u32 val;
130 val = readl(priv->glb_base + GLB_IRQ_ENA);
131 writel(val | irqs, priv->glb_base + GLB_IRQ_ENA);
136 u32 val;
138 val = readl(priv->glb_base + GLB_IRQ_ENA);
139 writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA);
157 u32 val;
161 val = readl(priv->port_base + ADDRQ_STAT) & TX_CNT_INUSE_MASK;
162 while (val < priv->tx_fifo_used_cnt) {
166 val, priv->tx_fifo_used_cnt);
176 val = readl(priv->port_base + ADDRQ_STAT) & TX_CNT_INUSE_MASK;
445 u32 val;
447 val = readl(priv->glb_base + GLB_SOFT_RESET);
448 val |= SOFT_RESET_ALL;
449 writel(val, priv->glb_base + GLB_SOFT_RESET);
453 val &= ~SOFT_RESET_ALL;
454 writel(val, priv->glb_base + GLB_SOFT_RESET);
505 u32 val;
507 val = readl(priv->port_base + ADDRQ_STAT);
508 val &= BIT_TX_READY;
509 if (!val) {
569 u32 val;
571 val = readl(priv->glb_base + GLB_MAC_H16(reg_n));
573 val |= BIT_MACFLT_ENA;
575 val &= ~BIT_MACFLT_ENA;
576 writel(val, priv->glb_base + GLB_MAC_H16(reg_n));
584 u32 val;
589 val = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
590 writel(val, priv->glb_base + low);
592 val = readl(priv->glb_base + high);
593 val &= ~MACFLT_HI16_MASK;
594 val |= ((addr[0] << 8) | addr[1]);
595 val |= (BIT_MACFLT_ENA | BIT_MACFLT_FW2CPU);
596 writel(val, priv->glb_base + high);
602 u32 val;
604 val = readl(priv->glb_base + GLB_FWCTRL);
606 val |= FWCTRL_FWALL2CPU;
608 val &= ~FWCTRL_FWALL2CPU;
609 writel(val, priv->glb_base + GLB_FWCTRL);
616 u32 val;
618 val = readl(priv->glb_base + GLB_MACTCTRL);
621 val |= MACTCTRL_MULTI2CPU;
634 val &= ~MACTCTRL_MULTI2CPU;
636 writel(val, priv->glb_base + GLB_MACTCTRL);
643 u32 val;
645 val = readl(priv->glb_base + GLB_MACTCTRL);
647 val |= MACTCTRL_UNI2CPU;
660 val &= ~MACTCTRL_UNI2CPU;
662 writel(val, priv->glb_base + GLB_MACTCTRL);
734 u32 val;
737 val = MAC_PORTSEL_STAT_CPU;
739 val |= MAC_PORTSEL_RMII;
740 writel(val, priv->port_base + MAC_PORTSEL);
746 val = readl(priv->glb_base + GLB_FWCTRL);
747 val &= ~(FWCTRL_VLAN_ENABLE | FWCTRL_FWALL2CPU);
748 val |= FWCTRL_FW2CPU_ENA;
749 writel(val, priv->glb_base + GLB_FWCTRL);
751 val = readl(priv->glb_base + GLB_MACTCTRL);
752 val |= (MACTCTRL_BROAD2CPU | MACTCTRL_MACT_ENA);
753 writel(val, priv->glb_base + GLB_MACTCTRL);
755 val = readl(priv->port_base + MAC_SET);
756 val &= ~MAX_FRAME_SIZE_MASK;
757 val |= MAX_FRAME_SIZE;
758 writel(val, priv->port_base + MAC_SET);
760 val = RX_COALESCED_TIMER |
762 writel(val, priv->port_base + RX_COALESCE_SET);
764 val = (HW_RX_FIFO_DEPTH << RX_DEPTH_OFFSET) | HW_TX_FIFO_DEPTH;
765 writel(val, priv->port_base + QLEN_SET);