Lines Matching refs:val
259 u32 val;
267 val = SGMII_SPEED_1000;
269 val = SGMII_SPEED_100;
271 val = SGMII_SPEED_10;
275 val = MII_SPEED_100;
277 val = MII_SPEED_10;
281 val = MII_SPEED_10;
284 writel_relaxed(val, priv->base + GE_PORT_MODE);
286 val = duplex ? GE_DUPLEX_FULL : GE_DUPLEX_HALF;
287 writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
289 val = GE_MODE_CHANGE_EN;
290 writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);
302 u32 val, tmp, timeout = 0;
305 regmap_read(priv->map, priv->port * 4 + PPE_CURR_BUF_CNT, &val);
309 } while (val & 0xfff);
314 u32 val;
316 val = readl_relaxed(priv->base + PPE_CFG_STS_MODE);
317 val |= PPE_CFG_STS_RX_PKT_CNT_RC;
318 writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);
320 val = BIT(priv->group);
321 regmap_write(priv->map, priv->port * 4 + PPE_CFG_POOL_GRP, val);
323 val = priv->group << PPE_CFG_QOS_VMID_GRP_SHIFT;
324 val |= PPE_CFG_QOS_VMID_MODE;
325 writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);
327 val = RX_BUF_SIZE >> PPE_BUF_SIZE_SHIFT;
328 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_BUF_SIZE, val);
330 val = RX_DESC_NUM << PPE_CFG_RX_DEPTH_SHIFT;
331 val |= PPE_CFG_RX_FIFO_FSFU;
332 val |= priv->chan << PPE_CFG_RX_START_SHIFT;
333 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_FIFO_SIZE, val);
335 val = NET_IP_ALIGN << PPE_CFG_RX_CTRL_ALIGN_SHIFT;
336 writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);
338 val = PPE_CFG_RX_PKT_ALIGN;
339 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
341 val = PPE_CFG_BUS_LOCAL_REL | PPE_CFG_BUS_BIG_ENDIEN;
342 writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
344 val = GMAC_PPE_RX_PKT_MAX_LEN;
345 writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
347 val = GMAC_MAX_PKT_LEN;
348 writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
350 val = GMAC_MIN_PKT_LEN;
351 writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
353 val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);
354 val |= GE_TX_AUTO_NEG | GE_TX_ADD_CRC | GE_TX_SHORT_PAD_THROUGH;
355 writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
357 val = GE_RX_STRIP_CRC;
358 writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
360 val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);
361 val |= GE_RX_STRIP_PAD | GE_RX_PAD_EN;
362 writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
365 val = GE_AUTO_NEG_CTL;
366 writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
373 u32 val;
376 val = readl_relaxed(priv->base + GE_PORT_EN);
377 val |= GE_RX_PORT_EN | GE_TX_PORT_EN;
378 writel_relaxed(val, priv->base + GE_PORT_EN);
381 val = RCV_INT;
382 writel_relaxed(val, priv->base + PPE_RINT);
385 val = GE_RX_INT_THRESHOLD | GE_RX_TIMEOUT;
386 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);
396 u32 val;
403 val = readl_relaxed(priv->base + GE_PORT_EN);
404 val &= ~(GE_RX_PORT_EN | GE_TX_PORT_EN);
405 writel_relaxed(val, priv->base + GE_PORT_EN);
410 u32 val;
412 val = phys >> PPE_BUF_SIZE_SHIFT | PPE_TX_BUF_HOLD;
413 writel(val, priv->base + PPE_CFG_CPU_ADD_ADDR);
418 u32 val;
420 val = phys >> PPE_BUF_SIZE_SHIFT;
421 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, val);