Lines Matching refs:base
210 void __iomem *base;
284 writel_relaxed(val, priv->base + GE_PORT_MODE);
287 writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
290 writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);
316 val = readl_relaxed(priv->base + PPE_CFG_STS_MODE);
318 writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);
325 writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);
336 writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);
339 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
342 writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
345 writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
348 writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
351 writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
353 val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);
355 writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
358 writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
360 val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);
362 writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
366 writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
376 val = readl_relaxed(priv->base + GE_PORT_EN);
378 writel_relaxed(val, priv->base + GE_PORT_EN);
382 writel_relaxed(val, priv->base + PPE_RINT);
386 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);
390 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
400 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
403 val = readl_relaxed(priv->base + GE_PORT_EN);
405 writel_relaxed(val, priv->base + GE_PORT_EN);
413 writel(val, priv->base + PPE_CFG_CPU_ADD_ADDR);
426 return readl(priv->base + PPE_HIS_RX_PKT_CNT);
434 priv->base + GE_STATION_MAC_ADDRESS);
437 priv->base + GE_STATION_MAC_ADDRESS + 4);
562 priv->base + PPE_INTEN);
650 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
666 u32 ists = readl_relaxed(priv->base + PPE_INTSTS);
671 writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);
688 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
705 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
909 priv->base = devm_platform_ioremap_resource(pdev, 0);
910 if (IS_ERR(priv->base)) {
911 ret = PTR_ERR(priv->base);