Lines Matching refs:fep
93 * @fep: the fec_enet_private structure handle
98 static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable)
106 if (fep->pps_enable == enable)
109 fep->pps_channel = DEFAULT_PPS_CHANNEL;
110 fep->reload_period = PPS_OUPUT_RELOAD_PERIOD;
112 spin_lock_irqsave(&fep->tmreg_lock, flags);
117 writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel));
123 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
126 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
127 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
131 timecounter_read(&fep->tc);
139 tempval = fep->cc.read(&fep->cc);
141 ns = timecounter_cyc2time(&fep->tc, tempval);
166 * is bigger than fep->cc.mask would be a error.
168 val &= fep->cc.mask;
169 writel(val, fep->hwp + FEC_TCCR(fep->pps_channel));
172 fep->next_counter = (val + fep->reload_period) & fep->cc.mask;
175 val = readl(fep->hwp + FEC_ATIME_CTRL);
177 writel(val, fep->hwp + FEC_ATIME_CTRL);
180 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
185 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
190 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
191 fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
193 writel(0, fep->hwp + FEC_TCSR(fep->pps_channel));
196 fep->pps_enable = enable;
197 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
212 struct fec_enet_private *fep =
216 tempval = readl(fep->hwp + FEC_ATIME_CTRL);
218 writel(tempval, fep->hwp + FEC_ATIME_CTRL);
220 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE)
223 return readl(fep->hwp + FEC_ATIME);
236 struct fec_enet_private *fep = netdev_priv(ndev);
240 inc = 1000000000 / fep->cycle_speed;
243 spin_lock_irqsave(&fep->tmreg_lock, flags);
246 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);
249 writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD);
252 fep->hwp + FEC_ATIME_CTRL);
254 memset(&fep->cc, 0, sizeof(fep->cc));
255 fep->cc.read = fec_ptp_read;
256 fep->cc.mask = CLOCKSOURCE_MASK(31);
257 fep->cc.shift = 31;
258 fep->cc.mult = FEC_CC_MULT;
261 timecounter_init(&fep->tc, &fep->cc, 0);
263 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
286 struct fec_enet_private *fep =
298 * Try to find the corr_inc between 1 to fep->ptp_inc to
302 rhs = (u64)ppb * (u64)fep->ptp_inc;
303 for (i = 1; i <= fep->ptp_inc; i++) {
314 if (i > fep->ptp_inc) {
315 corr_inc = fep->ptp_inc;
320 corr_ns = fep->ptp_inc - corr_inc;
322 corr_ns = fep->ptp_inc + corr_inc;
324 spin_lock_irqsave(&fep->tmreg_lock, flags);
326 tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
328 writel(tmp, fep->hwp + FEC_ATIME_INC);
330 writel(corr_period, fep->hwp + FEC_ATIME_CORR);
332 timecounter_read(&fep->tc);
334 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
348 struct fec_enet_private *fep =
352 spin_lock_irqsave(&fep->tmreg_lock, flags);
353 timecounter_adjtime(&fep->tc, delta);
354 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
401 struct fec_enet_private *fep =
408 mutex_lock(&fep->ptp_clk_mutex);
410 if (!fep->ptp_clk_on) {
411 mutex_unlock(&fep->ptp_clk_mutex);
419 counter = ns & fep->cc.mask;
421 spin_lock_irqsave(&fep->tmreg_lock, flags);
422 writel(counter, fep->hwp + FEC_ATIME);
423 timecounter_init(&fep->tc, &fep->cc, ns);
424 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
425 mutex_unlock(&fep->ptp_clk_mutex);
439 struct fec_enet_private *fep =
444 ret = fec_ptp_enable_pps(fep, on);
457 struct fec_enet_private *fep = netdev_priv(ndev);
459 fep->hwts_tx_en = 0;
460 fep->hwts_rx_en = 0;
465 struct fec_enet_private *fep = netdev_priv(ndev);
478 fep->hwts_tx_en = 0;
481 fep->hwts_tx_en = 1;
489 fep->hwts_rx_en = 0;
493 fep->hwts_rx_en = 1;
504 struct fec_enet_private *fep = netdev_priv(ndev);
508 config.tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
509 config.rx_filter = (fep->hwts_rx_en ?
523 struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep);
526 mutex_lock(&fep->ptp_clk_mutex);
527 if (fep->ptp_clk_on) {
528 spin_lock_irqsave(&fep->tmreg_lock, flags);
529 timecounter_read(&fep->tc);
530 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
532 mutex_unlock(&fep->ptp_clk_mutex);
534 schedule_delayed_work(&fep->time_keep, HZ);
541 struct fec_enet_private *fep = netdev_priv(ndev);
543 u8 channel = fep->pps_channel;
546 val = readl(fep->hwp + FEC_TCSR(channel));
551 writel(fep->next_counter, fep->hwp + FEC_TCCR(channel));
553 writel(val, fep->hwp + FEC_TCSR(channel));
554 } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK);
557 fep->next_counter = (fep->next_counter + fep->reload_period) &
558 fep->cc.mask;
561 ptp_clock_event(fep->ptp_clock, &event);
581 struct fec_enet_private *fep = netdev_priv(ndev);
585 fep->ptp_caps.owner = THIS_MODULE;
586 strlcpy(fep->ptp_caps.name, "fec ptp", sizeof(fep->ptp_caps.name));
588 fep->ptp_caps.max_adj = 250000000;
589 fep->ptp_caps.n_alarm = 0;
590 fep->ptp_caps.n_ext_ts = 0;
591 fep->ptp_caps.n_per_out = 0;
592 fep->ptp_caps.n_pins = 0;
593 fep->ptp_caps.pps = 1;
594 fep->ptp_caps.adjfreq = fec_ptp_adjfreq;
595 fep->ptp_caps.adjtime = fec_ptp_adjtime;
596 fep->ptp_caps.gettime64 = fec_ptp_gettime;
597 fep->ptp_caps.settime64 = fec_ptp_settime;
598 fep->ptp_caps.enable = fec_ptp_enable;
600 fep->cycle_speed = clk_get_rate(fep->clk_ptp);
601 if (!fep->cycle_speed) {
602 fep->cycle_speed = NSEC_PER_SEC;
603 dev_err(&fep->pdev->dev, "clk_ptp clock rate is zero\n");
605 fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed;
607 spin_lock_init(&fep->tmreg_lock);
611 INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep);
627 fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev);
628 if (IS_ERR(fep->ptp_clock)) {
629 fep->ptp_clock = NULL;
633 schedule_delayed_work(&fep->time_keep, HZ);
639 struct fec_enet_private *fep = netdev_priv(ndev);
641 cancel_delayed_work_sync(&fep->time_keep);
642 if (fep->ptp_clock)
643 ptp_clock_unregister(fep->ptp_clock);