Lines Matching refs:db
226 static void phy_write_1bit(struct uli526x_board_info *db, u32);
227 static u16 phy_read_1bit(struct uli526x_board_info *db);
239 static void srom_clk_write(struct uli526x_board_info *db, u32 data)
241 void __iomem *ioaddr = db->ioaddr;
272 struct uli526x_board_info *db; /* board information structure */
280 dev = alloc_etherdev(sizeof(*db));
315 db = netdev_priv(dev);
320 db->desc_pool_ptr = dma_alloc_coherent(&pdev->dev,
322 &db->desc_pool_dma_ptr, GFP_KERNEL);
323 if (!db->desc_pool_ptr)
326 db->buf_pool_ptr = dma_alloc_coherent(&pdev->dev,
328 &db->buf_pool_dma_ptr, GFP_KERNEL);
329 if (!db->buf_pool_ptr)
332 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
333 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
334 db->buf_pool_start = db->buf_pool_ptr;
335 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
339 db->phy.write = phy_writeby_cr10;
340 db->phy.read = phy_readby_cr10;
343 db->phy.write = phy_writeby_cr9;
344 db->phy.read = phy_readby_cr9;
353 db->ioaddr = ioaddr;
354 db->pdev = pdev;
355 db->init = 1;
363 spin_lock_init(&db->lock);
368 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i));
371 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
391 dev->dev_addr[i] = db->srom[20 + i];
406 pci_iounmap(pdev, db->ioaddr);
409 db->buf_pool_ptr, db->buf_pool_dma_ptr);
413 db->desc_pool_ptr, db->desc_pool_dma_ptr);
428 struct uli526x_board_info *db = netdev_priv(dev);
431 pci_iounmap(pdev, db->ioaddr);
432 dma_free_coherent(&db->pdev->dev,
434 db->desc_pool_ptr, db->desc_pool_dma_ptr);
435 dma_free_coherent(&db->pdev->dev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
436 db->buf_pool_ptr, db->buf_pool_dma_ptr);
451 struct uli526x_board_info *db = netdev_priv(dev);
456 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
457 db->tx_packet_cnt = 0;
458 db->rx_avail_cnt = 0;
459 db->link_failed = 1;
461 db->wait_reset = 0;
463 db->NIC_capability = 0xf; /* All capability*/
464 db->PHY_reg4 = 0x1e0;
467 db->cr6_data |= ULI526X_TXTH_256;
468 db->cr0_data = CR0_DEFAULT;
473 ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED,
482 timer_setup(&db->timer, uli526x_timer, 0);
483 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
484 add_timer(&db->timer);
499 struct uli526x_board_info *db = netdev_priv(dev);
500 struct uli_phy_ops *phy = &db->phy;
501 void __iomem *ioaddr = db->ioaddr;
512 uw32(DCR0, db->cr0_data);
516 db->phy_addr = 1;
520 phy_value = phy->read(db, phy_tmp, 3); //peer add
522 db->phy_addr = phy_tmp;
530 db->media_mode = uli526x_media_mode;
533 phy_reg_reset = phy->read(db, db->phy_addr, 0);
535 phy->write(db, db->phy_addr, 0, phy_reg_reset);
542 while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000)
546 uli526x_set_phyxcer(db);
549 if ( !(db->media_mode & ULI526X_AUTO) )
550 db->op_mode = db->media_mode; /* Force Mode */
556 update_cr6(db->cr6_data, ioaddr);
562 db->cr7_data = CR7_DEFAULT;
563 uw32(DCR7, db->cr7_data);
566 uw32(DCR15, db->cr15_data);
569 db->cr6_data |= CR6_RXSC | CR6_TXSC;
570 update_cr6(db->cr6_data, ioaddr);
582 struct uli526x_board_info *db = netdev_priv(dev);
583 void __iomem *ioaddr = db->ioaddr;
599 spin_lock_irqsave(&db->lock, flags);
602 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
603 spin_unlock_irqrestore(&db->lock, flags);
604 netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
612 txptr = db->tx_insert_ptr;
617 db->tx_insert_ptr = txptr->next_tx_desc;
620 if (db->tx_packet_cnt < TX_DESC_CNT) {
622 db->tx_packet_cnt++; /* Ready to send */
628 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
632 spin_unlock_irqrestore(&db->lock, flags);
633 uw32(DCR7, db->cr7_data);
649 struct uli526x_board_info *db = netdev_priv(dev);
650 void __iomem *ioaddr = db->ioaddr;
656 del_timer_sync(&db->timer);
661 db->phy.write(db, db->phy_addr, 0, 0x8000);
664 free_irq(db->pdev->irq, dev);
667 uli526x_free_rxbuffer(db);
681 struct uli526x_board_info *db = netdev_priv(dev);
682 void __iomem *ioaddr = db->ioaddr;
685 spin_lock_irqsave(&db->lock, flags);
689 db->cr5_data = ur32(DCR5);
690 uw32(DCR5, db->cr5_data);
691 if ( !(db->cr5_data & 0x180c1) ) {
693 uw32(DCR7, db->cr7_data);
694 spin_unlock_irqrestore(&db->lock, flags);
699 if (db->cr5_data & 0x2000) {
701 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
702 db->reset_fatal++;
703 db->wait_reset = 1; /* Need to RESET */
704 spin_unlock_irqrestore(&db->lock, flags);
709 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
710 uli526x_rx_packet(dev, db);
713 if (db->rx_avail_cnt<RX_DESC_CNT)
717 if ( db->cr5_data & 0x01)
718 uli526x_free_tx_pkt(dev, db);
721 uw32(DCR7, db->cr7_data);
723 spin_unlock_irqrestore(&db->lock, flags);
730 struct uli526x_board_info *db = netdev_priv(dev);
733 uli526x_interrupt(db->pdev->irq, dev);
742 struct uli526x_board_info * db)
747 txptr = db->tx_remove_ptr;
748 while(db->tx_packet_cnt) {
754 db->tx_packet_cnt--;
764 db->tx_fifo_underrun++;
765 if ( !(db->cr6_data & CR6_SFT) ) {
766 db->cr6_data = db->cr6_data | CR6_SFT;
767 update_cr6(db->cr6_data, db->ioaddr);
771 db->tx_excessive_collision++;
773 db->tx_late_collision++;
775 db->tx_no_carrier++;
777 db->tx_loss_carrier++;
779 db->tx_jabber_timeout++;
787 db->tx_remove_ptr = txptr;
790 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
799 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
806 rxptr = db->rx_ready_ptr;
808 while(db->rx_avail_cnt) {
815 db->rx_avail_cnt--;
816 db->interval_rx_cnt++;
818 dma_unmap_single(&db->pdev->dev, le32_to_cpu(rxptr->rdes2),
824 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
842 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
857 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
869 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
876 db->rx_ready_ptr = rxptr;
886 struct uli526x_board_info *db = netdev_priv(dev);
890 spin_lock_irqsave(&db->lock, flags);
894 db->cr6_data |= CR6_PM | CR6_PBF;
895 update_cr6(db->cr6_data, db->ioaddr);
896 spin_unlock_irqrestore(&db->lock, flags);
904 db->cr6_data &= ~(CR6_PM | CR6_PBF);
905 db->cr6_data |= CR6_PAM;
906 spin_unlock_irqrestore(&db->lock, flags);
912 spin_unlock_irqrestore(&db->lock, flags);
916 ULi_ethtool_get_link_ksettings(struct uli526x_board_info *db,
941 cmd->base.phy_address = db->phy_addr;
946 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
950 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
954 if(db->link_failed)
960 if (db->media_mode & ULI526X_AUTO)
1014 struct uli526x_board_info *db = from_timer(db, t, timer);
1015 struct net_device *dev = pci_get_drvdata(db->pdev);
1016 struct uli_phy_ops *phy = &db->phy;
1017 void __iomem *ioaddr = db->ioaddr;
1023 spin_lock_irqsave(&db->lock, flags);
1028 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1029 db->reset_cr8++;
1030 db->wait_reset = 1;
1032 db->interval_rx_cnt = 0;
1035 if ( db->tx_packet_cnt &&
1041 db->reset_TXtimeout++;
1042 db->wait_reset = 1;
1047 if (db->wait_reset) {
1048 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1049 db->reset_count++;
1051 db->timer.expires = ULI526X_TIMER_WUT;
1052 add_timer(&db->timer);
1053 spin_unlock_irqrestore(&db->lock, flags);
1058 if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0)
1061 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1066 db->link_failed = 1;
1070 if ( !(db->media_mode & 0x8) )
1071 phy->write(db, db->phy_addr, 0, 0x1000);
1074 if (db->media_mode & ULI526X_AUTO) {
1075 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1076 update_cr6(db->cr6_data, db->ioaddr);
1079 if ((tmp_cr12 & 0x3) && db->link_failed) {
1081 db->link_failed = 0;
1084 if ( (db->media_mode & ULI526X_AUTO) &&
1085 uli526x_sense_speed(db) )
1086 db->link_failed = 1;
1087 uli526x_process_mode(db);
1089 if(db->link_failed==0)
1092 (db->op_mode == ULI526X_100MHF ||
1093 db->op_mode == ULI526X_100MFD)
1095 (db->op_mode == ULI526X_10MFD ||
1096 db->op_mode == ULI526X_100MFD)
1100 /* SHOW_MEDIA_TYPE(db->op_mode); */
1102 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1104 if(db->init==1)
1110 db->init = 0;
1113 db->timer.expires = ULI526X_TIMER_WUT;
1114 add_timer(&db->timer);
1115 spin_unlock_irqrestore(&db->lock, flags);
1127 struct uli526x_board_info *db = netdev_priv(dev);
1128 void __iomem *ioaddr = db->ioaddr;
1131 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1132 update_cr6(db->cr6_data, ioaddr);
1140 uli526x_free_rxbuffer(db);
1143 db->tx_packet_cnt = 0;
1144 db->rx_avail_cnt = 0;
1145 db->link_failed = 1;
1146 db->init=1;
1147 db->wait_reset = 0;
1220 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1225 while (db->rx_avail_cnt) {
1226 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1227 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1228 db->rx_avail_cnt--;
1237 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1239 struct rx_desc *rxptr = db->rx_insert_ptr;
1243 rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb_tail_pointer(skb),
1247 db->rx_avail_cnt++;
1248 db->rx_insert_ptr = rxptr->next_rx_desc;
1250 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1261 struct uli526x_board_info *db = netdev_priv(dev);
1272 db->tx_insert_ptr = db->first_tx_desc;
1273 db->tx_remove_ptr = db->first_tx_desc;
1274 uw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
1277 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1278 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1279 db->rx_insert_ptr = db->first_rx_desc;
1280 db->rx_ready_ptr = db->first_rx_desc;
1281 uw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
1284 tmp_buf = db->buf_pool_start;
1285 tmp_buf_dma = db->buf_pool_dma_start;
1286 tmp_tx_dma = db->first_tx_desc_dma;
1287 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1298 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1299 tmp_tx->next_tx_desc = db->first_tx_desc;
1302 tmp_rx_dma=db->first_rx_desc_dma;
1303 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1310 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1311 tmp_rx->next_rx_desc = db->first_rx_desc;
1342 struct uli526x_board_info *db = netdev_priv(dev);
1343 void __iomem *ioaddr = db->ioaddr;
1352 txptr = db->tx_insert_ptr;
1381 db->tx_insert_ptr = txptr->next_tx_desc;
1385 if (db->tx_packet_cnt < TX_DESC_CNT) {
1387 db->tx_packet_cnt++;
1389 update_cr6(db->cr6_data | 0x2000, ioaddr);
1391 update_cr6(db->cr6_data, ioaddr);
1405 struct uli526x_board_info *db = netdev_priv(dev);
1409 rxptr = db->rx_insert_ptr;
1411 while(db->rx_avail_cnt < RX_DESC_CNT) {
1416 rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb_tail_pointer(skb),
1421 db->rx_avail_cnt++;
1424 db->rx_insert_ptr = rxptr;
1432 static u16 read_srom_word(struct uli526x_board_info *db, int offset)
1434 void __iomem *ioaddr = db->ioaddr;
1442 srom_clk_write(db, SROM_DATA_1);
1443 srom_clk_write(db, SROM_DATA_1);
1444 srom_clk_write(db, SROM_DATA_0);
1449 srom_clk_write(db, srom_data);
1472 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1474 struct uli_phy_ops *phy = &db->phy;
1478 phy_mode = phy->read(db, db->phy_addr, 1);
1479 phy_mode = phy->read(db, db->phy_addr, 1);
1483 phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7);
1494 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1495 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1496 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1497 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1498 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1501 db->op_mode = ULI526X_10MHF;
1516 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1518 struct uli_phy_ops *phy = &db->phy;
1522 phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0;
1524 if (db->media_mode & ULI526X_AUTO) {
1526 phy_reg |= db->PHY_reg4;
1529 switch(db->media_mode) {
1540 phy_reg|=db->PHY_reg4;
1541 db->media_mode|=ULI526X_AUTO;
1543 phy->write(db, db->phy_addr, 4, phy_reg);
1546 phy->write(db, db->phy_addr, 0, 0x1200);
1558 static void uli526x_process_mode(struct uli526x_board_info *db)
1560 struct uli_phy_ops *phy = &db->phy;
1564 if (db->op_mode & 0x4)
1565 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1567 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1569 update_cr6(db->cr6_data, db->ioaddr);
1572 if (!(db->media_mode & 0x8)) {
1574 phy_reg = phy->read(db, db->phy_addr, 6);
1578 switch(db->op_mode) {
1584 phy->write(db, db->phy_addr, 0, phy_reg);
1591 static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr,
1598 phy_write_1bit(db, PHY_DATA_1);
1601 phy_write_1bit(db, PHY_DATA_0);
1602 phy_write_1bit(db, PHY_DATA_1);
1605 phy_write_1bit(db, PHY_DATA_0);
1606 phy_write_1bit(db, PHY_DATA_1);
1610 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1614 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1617 phy_write_1bit(db, PHY_DATA_1);
1618 phy_write_1bit(db, PHY_DATA_0);
1622 phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1625 static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset)
1632 phy_write_1bit(db, PHY_DATA_1);
1635 phy_write_1bit(db, PHY_DATA_0);
1636 phy_write_1bit(db, PHY_DATA_1);
1639 phy_write_1bit(db, PHY_DATA_1);
1640 phy_write_1bit(db, PHY_DATA_0);
1644 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1648 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1651 phy_read_1bit(db);
1656 phy_data |= phy_read_1bit(db);
1662 static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1665 void __iomem *ioaddr = db->ioaddr;
1680 static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1683 void __iomem *ioaddr = db->ioaddr;
1695 static void phy_write_1bit(struct uli526x_board_info *db, u32 data)
1697 void __iomem *ioaddr = db->ioaddr;
1712 static u16 phy_read_1bit(struct uli526x_board_info *db)
1714 void __iomem *ioaddr = db->ioaddr;