Lines Matching defs:uw32
35 #define uw32(reg, val) iowrite32(val, ioaddr + (reg))
243 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
245 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
247 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
373 uw32(DCR0, 0x10000); //Diagnosis mode
374 uw32(DCR13, 0x1c0); //Reset dianostic pointer port
375 uw32(DCR14, 0); //Clear reset port
376 uw32(DCR14, 0x10); //Reset ID Table pointer
377 uw32(DCR14, 0); //Clear reset port
378 uw32(DCR13, 0); //Clear CR13
379 uw32(DCR13, 0x1b0); //Select ID Table access port
384 uw32(DCR13, 0); //Clear CR13
385 uw32(DCR0, 0); //Clear CR0
510 uw32(DCR0, ULI526X_RESET); /* RESET MAC */
512 uw32(DCR0, db->cr0_data);
563 uw32(DCR7, db->cr7_data);
566 uw32(DCR15, db->cr15_data);
609 uw32(DCR7, 0);
623 uw32(DCR1, 0x1); /* Issue Tx polling */
633 uw32(DCR7, db->cr7_data);
659 uw32(DCR0, ULI526X_RESET);
686 uw32(DCR7, 0);
690 uw32(DCR5, db->cr5_data);
693 uw32(DCR7, db->cr7_data);
721 uw32(DCR7, db->cr7_data);
1037 uw32(DCR1, 0x1); // Tx polling again
1133 uw32(DCR7, 0); /* Disable Interrupt */
1134 uw32(DCR5, ur32(DCR5));
1274 uw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
1281 uw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
1324 uw32(DCR6, cr6_data);
1390 uw32(DCR1, 0x1); /* Issue Tx polling */
1438 uw32(DCR9, CR9_SROM_READ);
1439 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1452 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1455 uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
1459 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1463 uw32(DCR9, CR9_SROM_READ);
1670 uw32(DCR10, cr10_value);
1688 uw32(DCR10, cr10_value);
1699 uw32(DCR9, data); /* MII Clock Low */
1701 uw32(DCR9, data | MDCLKH); /* MII Clock High */
1703 uw32(DCR9, data); /* MII Clock Low */
1717 uw32(DCR9, 0x50000);
1720 uw32(DCR9, 0x40000);