Lines Matching refs:db
354 struct dmfe_board_info *db; /* board information structure */
378 dev = alloc_etherdev(sizeof(*db));
422 db = netdev_priv(dev);
425 db->desc_pool_ptr = dma_alloc_coherent(&pdev->dev,
427 &db->desc_pool_dma_ptr, GFP_KERNEL);
428 if (!db->desc_pool_ptr) {
433 db->buf_pool_ptr = dma_alloc_coherent(&pdev->dev,
435 &db->buf_pool_dma_ptr, GFP_KERNEL);
436 if (!db->buf_pool_ptr) {
441 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
442 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
443 db->buf_pool_start = db->buf_pool_ptr;
444 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
446 db->chip_id = ent->driver_data;
448 db->ioaddr = pci_iomap(pdev, 0, 0);
449 if (!db->ioaddr) {
454 db->chip_revision = pdev->revision;
455 db->wol_mode = 0;
457 db->pdev = pdev;
463 spin_lock_init(&db->lock);
467 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
468 db->chip_type = 1; /* DM9102A E3 */
470 db->chip_type = 0;
474 ((__le16 *) db->srom)[i] =
475 cpu_to_le16(read_srom_word(db->ioaddr, i));
480 dev->dev_addr[i] = db->srom[20 + i];
495 pci_iounmap(pdev, db->ioaddr);
498 db->buf_pool_ptr, db->buf_pool_dma_ptr);
502 db->desc_pool_ptr, db->desc_pool_dma_ptr);
517 struct dmfe_board_info *db = netdev_priv(dev);
524 pci_iounmap(db->pdev, db->ioaddr);
525 dma_free_coherent(&db->pdev->dev,
527 db->desc_pool_ptr, db->desc_pool_dma_ptr);
528 dma_free_coherent(&db->pdev->dev,
530 db->buf_pool_ptr, db->buf_pool_dma_ptr);
546 struct dmfe_board_info *db = netdev_priv(dev);
547 const int irq = db->pdev->irq;
557 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
558 db->tx_packet_cnt = 0;
559 db->tx_queue_cnt = 0;
560 db->rx_avail_cnt = 0;
561 db->wait_reset = 0;
563 db->first_in_callback = 0;
564 db->NIC_capability = 0xf; /* All capability*/
565 db->PHY_reg4 = 0x1e0;
568 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
569 (db->chip_revision >= 0x30) ) {
570 db->cr6_data |= DMFE_TXTH_256;
571 db->cr0_data = CR0_DEFAULT;
572 db->dm910x_chk_mode=4; /* Enter the normal mode */
574 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
575 db->cr0_data = 0;
576 db->dm910x_chk_mode = 1; /* Enter the check mode */
586 timer_setup(&db->timer, dmfe_timer, 0);
587 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
588 add_timer(&db->timer);
603 struct dmfe_board_info *db = netdev_priv(dev);
604 void __iomem *ioaddr = db->ioaddr;
611 dw32(DCR0, db->cr0_data);
615 db->phy_addr = 1;
618 dmfe_parse_srom(db);
619 db->media_mode = dmfe_media_mode;
623 if (db->chip_id == PCI_DM9009_ID) {
630 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
631 dmfe_set_phyxcer(db);
634 if ( !(db->media_mode & DMFE_AUTO) )
635 db->op_mode = db->media_mode; /* Force Mode */
641 update_cr6(db->cr6_data, ioaddr);
644 if (db->chip_id == PCI_DM9132_ID)
650 db->cr7_data = CR7_DEFAULT;
651 dw32(DCR7, db->cr7_data);
654 dw32(DCR15, db->cr15_data);
657 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
658 update_cr6(db->cr6_data, ioaddr);
670 struct dmfe_board_info *db = netdev_priv(dev);
671 void __iomem *ioaddr = db->ioaddr;
687 spin_lock_irqsave(&db->lock, flags);
690 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
691 spin_unlock_irqrestore(&db->lock, flags);
692 pr_err("No Tx resource %ld\n", db->tx_queue_cnt);
700 txptr = db->tx_insert_ptr;
705 db->tx_insert_ptr = txptr->next_tx_desc;
708 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
710 db->tx_packet_cnt++; /* Ready to send */
714 db->tx_queue_cnt++; /* queue TX packet */
719 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
723 spin_unlock_irqrestore(&db->lock, flags);
724 dw32(DCR7, db->cr7_data);
740 struct dmfe_board_info *db = netdev_priv(dev);
741 void __iomem *ioaddr = db->ioaddr;
749 del_timer_sync(&db->timer);
754 dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
757 free_irq(db->pdev->irq, dev);
760 dmfe_free_rxbuffer(db);
765 db->tx_fifo_underrun, db->tx_excessive_collision,
766 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
767 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
768 db->reset_fatal, db->reset_TXtimeout);
783 struct dmfe_board_info *db = netdev_priv(dev);
784 void __iomem *ioaddr = db->ioaddr;
789 spin_lock_irqsave(&db->lock, flags);
792 db->cr5_data = dr32(DCR5);
793 dw32(DCR5, db->cr5_data);
794 if ( !(db->cr5_data & 0xc1) ) {
795 spin_unlock_irqrestore(&db->lock, flags);
803 if (db->cr5_data & 0x2000) {
805 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
806 db->reset_fatal++;
807 db->wait_reset = 1; /* Need to RESET */
808 spin_unlock_irqrestore(&db->lock, flags);
813 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
814 dmfe_rx_packet(dev, db);
817 if (db->rx_avail_cnt<RX_DESC_CNT)
821 if ( db->cr5_data & 0x01)
822 dmfe_free_tx_pkt(dev, db);
825 if (db->dm910x_chk_mode & 0x2) {
826 db->dm910x_chk_mode = 0x4;
827 db->cr6_data |= 0x100;
828 update_cr6(db->cr6_data, ioaddr);
832 dw32(DCR7, db->cr7_data);
834 spin_unlock_irqrestore(&db->lock, flags);
848 struct dmfe_board_info *db = netdev_priv(dev);
849 const int irq = db->pdev->irq;
863 static void dmfe_free_tx_pkt(struct net_device *dev, struct dmfe_board_info *db)
866 void __iomem *ioaddr = db->ioaddr;
869 txptr = db->tx_remove_ptr;
870 while(db->tx_packet_cnt) {
876 db->tx_packet_cnt--;
887 db->tx_fifo_underrun++;
888 if ( !(db->cr6_data & CR6_SFT) ) {
889 db->cr6_data = db->cr6_data | CR6_SFT;
890 update_cr6(db->cr6_data, ioaddr);
894 db->tx_excessive_collision++;
896 db->tx_late_collision++;
898 db->tx_no_carrier++;
900 db->tx_loss_carrier++;
902 db->tx_jabber_timeout++;
910 db->tx_remove_ptr = txptr;
913 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
915 db->tx_packet_cnt++; /* Ready to send */
916 db->tx_queue_cnt--;
922 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
945 static void dmfe_rx_packet(struct net_device *dev, struct dmfe_board_info *db)
952 rxptr = db->rx_ready_ptr;
954 while(db->rx_avail_cnt) {
959 db->rx_avail_cnt--;
960 db->interval_rx_cnt++;
962 dma_unmap_single(&db->pdev->dev, le32_to_cpu(rxptr->rdes2),
969 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
987 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
991 if ( (db->dm910x_chk_mode & 1) &&
995 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
996 db->dm910x_chk_mode = 3;
1010 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1022 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1029 db->rx_ready_ptr = rxptr;
1038 struct dmfe_board_info *db = netdev_priv(dev);
1043 spin_lock_irqsave(&db->lock, flags);
1047 db->cr6_data |= CR6_PM | CR6_PBF;
1048 update_cr6(db->cr6_data, db->ioaddr);
1049 spin_unlock_irqrestore(&db->lock, flags);
1055 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1056 db->cr6_data |= CR6_PAM;
1057 spin_unlock_irqrestore(&db->lock, flags);
1062 if (db->chip_id == PCI_DM9132_ID)
1066 spin_unlock_irqrestore(&db->lock, flags);
1085 struct dmfe_board_info *db = netdev_priv(dev);
1091 db->wol_mode = wolinfo->wolopts;
1098 struct dmfe_board_info *db = netdev_priv(dev);
1101 wolinfo->wolopts = db->wol_mode;
1119 struct dmfe_board_info *db = from_timer(db, t, timer);
1120 struct net_device *dev = pci_get_drvdata(db->pdev);
1121 void __iomem *ioaddr = db->ioaddr;
1129 spin_lock_irqsave(&db->lock, flags);
1132 if (db->first_in_callback == 0) {
1133 db->first_in_callback = 1;
1134 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1135 db->cr6_data &= ~0x40000;
1136 update_cr6(db->cr6_data, ioaddr);
1137 dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1138 db->cr6_data |= 0x40000;
1139 update_cr6(db->cr6_data, ioaddr);
1140 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1141 add_timer(&db->timer);
1142 spin_unlock_irqrestore(&db->lock, flags);
1149 if ( (db->dm910x_chk_mode & 0x1) &&
1151 db->dm910x_chk_mode = 0x4;
1155 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1156 db->reset_cr8++;
1157 db->wait_reset = 1;
1159 db->interval_rx_cnt = 0;
1162 if ( db->tx_packet_cnt &&
1168 db->reset_TXtimeout++;
1169 db->wait_reset = 1;
1174 if (db->wait_reset) {
1175 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1176 db->reset_count++;
1178 db->first_in_callback = 0;
1179 db->timer.expires = DMFE_TIMER_WUT;
1180 add_timer(&db->timer);
1181 spin_unlock_irqrestore(&db->lock, flags);
1186 if (db->chip_id == PCI_DM9132_ID)
1191 if ( ((db->chip_id == PCI_DM9102_ID) &&
1192 (db->chip_revision == 0x30)) ||
1193 ((db->chip_id == PCI_DM9132_ID) &&
1194 (db->chip_revision == 0x10)) ) {
1213 dmfe_phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1214 link_ok_phy = (dmfe_phy_read (db->ioaddr,
1215 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1229 if ( !(db->media_mode & 0x38) )
1230 dmfe_phy_write(db->ioaddr, db->phy_addr,
1231 0, 0x1000, db->chip_id);
1234 if (db->media_mode & DMFE_AUTO) {
1236 db->cr6_data|=0x00040000; /* bit18=1, MII */
1237 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1238 update_cr6(db->cr6_data, ioaddr);
1245 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1247 SHOW_MEDIA_TYPE(db->op_mode);
1250 dmfe_process_mode(db);
1254 if (db->HPNA_command & 0xf00) {
1255 db->HPNA_timer--;
1256 if (!db->HPNA_timer)
1257 dmfe_HPNA_remote_cmd_chk(db);
1261 db->timer.expires = DMFE_TIMER_WUT;
1262 add_timer(&db->timer);
1263 spin_unlock_irqrestore(&db->lock, flags);
1277 struct dmfe_board_info *db = netdev_priv(dev);
1278 void __iomem *ioaddr = db->ioaddr;
1283 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1284 update_cr6(db->cr6_data, ioaddr);
1292 dmfe_free_rxbuffer(db);
1295 db->tx_packet_cnt = 0;
1296 db->tx_queue_cnt = 0;
1297 db->rx_avail_cnt = 0;
1299 db->wait_reset = 0;
1313 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1318 while (db->rx_avail_cnt) {
1319 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1320 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1321 db->rx_avail_cnt--;
1330 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1332 struct rx_desc *rxptr = db->rx_insert_ptr;
1336 rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb->data,
1340 db->rx_avail_cnt++;
1341 db->rx_insert_ptr = rxptr->next_rx_desc;
1343 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1354 struct dmfe_board_info *db = netdev_priv(dev);
1355 void __iomem *ioaddr = db->ioaddr;
1366 db->tx_insert_ptr = db->first_tx_desc;
1367 db->tx_remove_ptr = db->first_tx_desc;
1368 dw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
1371 db->first_rx_desc = (void *)db->first_tx_desc +
1374 db->first_rx_desc_dma = db->first_tx_desc_dma +
1376 db->rx_insert_ptr = db->first_rx_desc;
1377 db->rx_ready_ptr = db->first_rx_desc;
1378 dw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
1381 tmp_buf = db->buf_pool_start;
1382 tmp_buf_dma = db->buf_pool_dma_start;
1383 tmp_tx_dma = db->first_tx_desc_dma;
1384 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1395 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1396 tmp_tx->next_tx_desc = db->first_tx_desc;
1399 tmp_rx_dma=db->first_rx_desc_dma;
1400 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1407 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1408 tmp_rx->next_rx_desc = db->first_rx_desc;
1439 struct dmfe_board_info *db = netdev_priv(dev);
1440 void __iomem *ioaddr = db->ioaddr + 0xc0;
1477 struct dmfe_board_info *db = netdev_priv(dev);
1486 txptr = db->tx_insert_ptr;
1515 db->tx_insert_ptr = txptr->next_tx_desc;
1519 if (!db->tx_packet_cnt) {
1520 void __iomem *ioaddr = db->ioaddr;
1523 db->tx_packet_cnt++;
1525 update_cr6(db->cr6_data | 0x2000, ioaddr);
1527 update_cr6(db->cr6_data, ioaddr);
1530 db->tx_queue_cnt++; /* Put in TX queue */
1541 struct dmfe_board_info *db = netdev_priv(dev);
1545 rxptr = db->rx_insert_ptr;
1547 while(db->rx_avail_cnt < RX_DESC_CNT) {
1551 rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb->data,
1556 db->rx_avail_cnt++;
1559 db->rx_insert_ptr = rxptr;
1623 static u8 dmfe_sense_speed(struct dmfe_board_info *db)
1625 void __iomem *ioaddr = db->ioaddr;
1630 update_cr6(db->cr6_data & ~0x40000, ioaddr);
1632 phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1633 phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1636 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1637 phy_mode = dmfe_phy_read(db->ioaddr,
1638 db->phy_addr, 7, db->chip_id) & 0xf000;
1640 phy_mode = dmfe_phy_read(db->ioaddr,
1641 db->phy_addr, 17, db->chip_id) & 0xf000;
1643 case 0x1000: db->op_mode = DMFE_10MHF; break;
1644 case 0x2000: db->op_mode = DMFE_10MFD; break;
1645 case 0x4000: db->op_mode = DMFE_100MHF; break;
1646 case 0x8000: db->op_mode = DMFE_100MFD; break;
1647 default: db->op_mode = DMFE_10MHF;
1652 db->op_mode = DMFE_10MHF;
1667 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1669 void __iomem *ioaddr = db->ioaddr;
1673 db->cr6_data &= ~0x40000;
1674 update_cr6(db->cr6_data, ioaddr);
1677 if (db->chip_id == PCI_DM9009_ID) {
1678 phy_reg = dmfe_phy_read(db->ioaddr,
1679 db->phy_addr, 18, db->chip_id) & ~0x1000;
1681 dmfe_phy_write(db->ioaddr,
1682 db->phy_addr, 18, phy_reg, db->chip_id);
1686 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1688 if (db->media_mode & DMFE_AUTO) {
1690 phy_reg |= db->PHY_reg4;
1693 switch(db->media_mode) {
1699 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1704 phy_reg|=db->PHY_reg4;
1705 db->media_mode|=DMFE_AUTO;
1707 dmfe_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1710 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1711 dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1712 if ( !db->chip_type )
1713 dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1724 static void dmfe_process_mode(struct dmfe_board_info *db)
1729 if (db->op_mode & 0x4)
1730 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1732 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1735 if (db->op_mode & 0x10) /* 1M HomePNA */
1736 db->cr6_data |= 0x40000;/* External MII select */
1738 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1740 update_cr6(db->cr6_data, db->ioaddr);
1743 if ( !(db->media_mode & 0x18)) {
1745 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1749 switch(db->op_mode) {
1755 dmfe_phy_write(db->ioaddr,
1756 db->phy_addr, 0, phy_reg, db->chip_id);
1757 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1759 dmfe_phy_write(db->ioaddr,
1760 db->phy_addr, 0, phy_reg, db->chip_id);
1902 static void dmfe_parse_srom(struct dmfe_board_info * db)
1904 char * srom = db->srom;
1910 db->cr15_data = CR15_DEFAULT;
1916 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1917 db->PHY_reg4 = 0;
1919 switch( db->NIC_capability & tmp_reg ) {
1920 case 0x1: db->PHY_reg4 |= 0x0020; break;
1921 case 0x2: db->PHY_reg4 |= 0x0040; break;
1922 case 0x4: db->PHY_reg4 |= 0x0080; break;
1923 case 0x8: db->PHY_reg4 |= 0x0100; break;
1941 db->cr15_data |= 0x40;
1945 db->cr15_data |= 0x400;
1949 db->cr15_data |= 0x9800;
1953 db->HPNA_command = 1;
1957 db->HPNA_command |= 0x8000;
1962 case 0: db->HPNA_command |= 0x0904; break;
1963 case 1: db->HPNA_command |= 0x0a00; break;
1964 case 2: db->HPNA_command |= 0x0506; break;
1965 case 3: db->HPNA_command |= 0x0602; break;
1969 case 0: db->HPNA_command |= 0x0004; break;
1970 case 1: db->HPNA_command |= 0x0000; break;
1971 case 2: db->HPNA_command |= 0x0006; break;
1972 case 3: db->HPNA_command |= 0x0002; break;
1976 db->HPNA_present = 0;
1977 update_cr6(db->cr6_data | 0x40000, db->ioaddr);
1978 tmp_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1981 db->HPNA_timer = 8;
1982 if ( dmfe_phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1984 db->HPNA_present = 1;
1985 dmfe_program_DM9801(db, tmp_reg);
1988 db->HPNA_present = 2;
1989 dmfe_program_DM9802(db);
2000 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2007 db->HPNA_command |= 0x1000;
2008 reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2010 reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2013 reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2015 reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2021 db->HPNA_command |= 0x1000;
2022 reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2024 reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2028 dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2029 dmfe_phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2030 dmfe_phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2038 static void dmfe_program_DM9802(struct dmfe_board_info * db)
2043 dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2044 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2046 dmfe_phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2055 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2060 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2069 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
2070 dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2071 db->chip_id);
2072 db->HPNA_timer=8;
2074 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2091 struct dmfe_board_info *db = netdev_priv(dev);
2092 void __iomem *ioaddr = db->ioaddr;
2098 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2099 update_cr6(db->cr6_data, ioaddr);
2106 dmfe_free_rxbuffer(db);