Lines Matching defs:dw32
143 #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
609 dw32(DCR0, DM910X_RESET); /* RESET MAC */
611 dw32(DCR0, db->cr0_data);
622 dw32(DCR12, 0x180); /* Let bit 7 output port */
624 dw32(DCR12, 0x80); /* Issue RESET signal */
627 dw32(DCR12, 0x0); /* Clear RESET signal */
651 dw32(DCR7, db->cr7_data);
654 dw32(DCR15, db->cr15_data);
697 dw32(DCR7, 0);
711 dw32(DCR1, 0x1); /* Issue Tx polling */
715 dw32(DCR1, 0x1); /* Issue Tx polling */
724 dw32(DCR7, db->cr7_data);
752 dw32(DCR0, DM910X_RESET);
793 dw32(DCR5, db->cr5_data);
800 dw32(DCR7, 0);
832 dw32(DCR7, db->cr7_data);
917 dw32(DCR1, 0x1); /* Issue Tx polling */
1164 dw32(DCR1, 0x1); /* Tx polling again */
1285 dw32(DCR7, 0); /* Disable Interrupt */
1286 dw32(DCR5, dr32(DCR5));
1368 dw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
1378 dw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
1425 dw32(DCR6, cr6_tmp);
1427 dw32(DCR6, cr6_data);
1526 dw32(DCR1, 0x1); /* Issue Tx polling */
1572 dw32(DCR9, data | cmd[i]);
1585 dw32(DCR9, CR9_SROM_READ);
1587 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1601 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1605 dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
1609 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1613 dw32(DCR9, CR9_SROM_READ);
1871 dw32(DCR9, phy_data); /* MII Clock Low */
1873 dw32(DCR9, phy_data | MDCLKH); /* MII Clock High */
1875 dw32(DCR9, phy_data); /* MII Clock Low */
1888 dw32(DCR9, 0x50000);
1891 dw32(DCR9, 0x40000);
2102 dw32(DCR7, 0);
2103 dw32(DCR5, dr32(DCR5));