Lines Matching refs:lp
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
343 Fix initialisation problem with lp->timeout in
404 lp->rst not run because lp->ibn not initialised -
420 Change dev->interrupt to lp->interrupt to ensure
682 imr |= lp->irq_en;\
688 imr &= ~lp->irq_en;\
693 imr |= lp->irq_mask;\
699 imr &= ~lp->irq_mask;\
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
954 static void PCI_signature(char *name, struct de4x5_private *lp);
957 static int de4x5_bad_srom(struct de4x5_private *lp);
985 static int an_exception(struct de4x5_private *lp);
1097 struct de4x5_private *lp = netdev_priv(dev);
1104 if (lp->bus == EISA) {
1121 lp->useSROM = false;
1122 if (lp->bus == PCI) {
1123 PCI_signature(name, lp);
1142 skb_queue_head_init(&lp->cache.queue);
1143 lp->cache.gepc = GEP_INIT;
1144 lp->asBit = GEP_SLNK;
1145 lp->asPolarity = GEP_SLNK;
1146 lp->asBitValid = ~0;
1147 lp->timeout = -1;
1148 lp->gendev = gendev;
1149 spin_lock_init(&lp->lock);
1150 timer_setup(&lp->timer, de4x5_ast, 0);
1156 lp->autosense = lp->params.autosense;
1157 if (lp->chipset != DC21140) {
1158 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1159 lp->params.autosense = TP;
1161 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1162 lp->params.autosense = BNC;
1165 lp->fdx = lp->params.fdx;
1166 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1168 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1170 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1172 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1173 &lp->dma_rings, GFP_ATOMIC);
1174 if (lp->rx_ring == NULL) {
1178 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1186 lp->rx_ring[i].status = 0;
1187 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1188 lp->rx_ring[i].buf = 0;
1189 lp->rx_ring[i].next = 0;
1190 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1197 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1200 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1203 lp->rx_ring[i].status = 0;
1204 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1205 lp->rx_ring[i].buf =
1207 lp->rx_ring[i].next = 0;
1208 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1216 lp->rxRingSize = NUM_RX_DESC;
1217 lp->txRingSize = NUM_TX_DESC;
1220 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1221 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1224 outl(lp->dma_rings, DE4X5_RRBA);
1225 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1229 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1230 lp->irq_en = IMR_NIM | IMR_AIM;
1233 create_packet(dev, lp->frame, sizeof(lp->frame));
1236 i = lp->cfrv & 0x000000fe;
1237 if ((lp->chipset == DC21140) && (i == 0x20)) {
1238 lp->rx_ovf = 1;
1242 if (lp->useSROM) {
1243 lp->state = INITIALISED;
1245 dma_free_coherent (gendev, lp->dma_size,
1246 lp->rx_ring, lp->dma_rings);
1252 lp->state = CLOSED;
1257 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1262 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1276 dma_free_coherent (gendev, lp->dma_size,
1277 lp->rx_ring, lp->dma_rings);
1291 struct de4x5_private *lp = netdev_priv(dev);
1297 for (i=0; i<lp->rxRingSize; i++) {
1313 spin_lock_init(&lp->lock);
1314 lp->state = OPEN;
1318 lp->adapter_name, dev)) {
1321 lp->adapter_name, dev)) {
1327 lp->state = CLOSED;
1335 lp->interrupt = UNMASK_INTERRUPTS;
1381 struct de4x5_private *lp = netdev_priv(dev);
1387 if (!lp->useSROM) {
1388 if (lp->phy[lp->active].id != 0) {
1389 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1391 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1401 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1402 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1406 if (lp->chipset == DC21140) {
1409 lp->setup_f = PERFECT;
1410 outl(lp->dma_rings, DE4X5_RRBA);
1411 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1414 lp->rx_new = lp->rx_old = 0;
1415 lp->tx_new = lp->tx_old = 0;
1417 for (i = 0; i < lp->rxRingSize; i++) {
1418 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1421 for (i = 0; i < lp->txRingSize; i++) {
1422 lp->tx_ring[i].status = cpu_to_le32(0);
1430 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1437 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1447 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1448 lp->tx_old = lp->tx_new;
1459 struct de4x5_private *lp = netdev_priv(dev);
1464 if (!lp->tx_enable) /* Cannot send for now */
1472 spin_lock_irqsave(&lp->lock, flags);
1474 spin_unlock_irqrestore(&lp->lock, flags);
1477 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1481 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1482 if (lp->interrupt) {
1488 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1492 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1498 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1499 spin_lock_irqsave(&lp->lock, flags);
1502 lp->stats.tx_bytes += skb->len;
1505 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1511 spin_unlock_irqrestore(&lp->lock, flags);
1516 lp->cache.lock = 0;
1539 struct de4x5_private *lp;
1544 lp = netdev_priv(dev);
1545 spin_lock(&lp->lock);
1550 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1559 if (!(sts & lp->irq_mask)) break;/* All done */
1569 lp->irq_mask &= ~IMR_LFM;
1580 spin_unlock(&lp->lock);
1586 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1587 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1590 lp->cache.lock = 0;
1593 lp->interrupt = UNMASK_INTERRUPTS;
1595 spin_unlock(&lp->lock);
1603 struct de4x5_private *lp = netdev_priv(dev);
1608 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1609 entry=lp->rx_new) {
1610 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1612 if (lp->rx_ovf) {
1620 lp->rx_old = entry;
1624 if (lp->tx_enable) lp->linkOK++;
1626 lp->stats.rx_errors++; /* Update the error stats. */
1627 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1628 if (status & RD_CE) lp->stats.rx_crc_errors++;
1629 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1630 if (status & RD_TL) lp->stats.rx_length_errors++;
1631 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1632 if (status & RD_CS) lp->pktStats.rx_collision++;
1633 if (status & RD_DB) lp->pktStats.rx_dribble++;
1634 if (status & RD_OF) lp->pktStats.rx_overflow++;
1637 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1643 lp->stats.rx_dropped++;
1653 lp->stats.rx_packets++;
1654 lp->stats.rx_bytes += pkt_len;
1659 for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old + 1)%lp->rxRingSize) {
1660 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1663 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1670 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1677 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1679 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1680 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1682 if ((u_long) lp->tx_skb[entry] > 1)
1683 dev_kfree_skb_irq(lp->tx_skb[entry]);
1684 lp->tx_skb[entry] = NULL;
1693 struct de4x5_private *lp = netdev_priv(dev);
1698 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1699 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1704 lp->stats.tx_errors++;
1705 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1706 if (status & TD_LC) lp->stats.tx_window_errors++;
1707 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1708 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1709 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1715 lp->stats.tx_packets++;
1716 if (lp->tx_enable) lp->linkOK++;
1719 lp->stats.collisions += ((status & TD_EC) ? 16 :
1723 if (lp->tx_skb[entry] != NULL)
1724 de4x5_free_tx_buff(lp, entry);
1728 lp->tx_old = (lp->tx_old + 1) % lp->txRingSize;
1733 if (lp->interrupt)
1745 struct de4x5_private *lp = from_timer(lp, t, timer);
1746 struct net_device *dev = dev_get_drvdata(lp->gendev);
1750 if (lp->useSROM)
1752 else if (lp->chipset == DC21140)
1754 else if (lp->chipset == DC21041)
1756 else if (lp->chipset == DC21040)
1758 lp->linkOK = 0;
1765 mod_timer(&lp->timer, jiffies + dt);
1771 struct de4x5_private *lp = netdev_priv(dev);
1776 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1794 struct de4x5_private *lp = netdev_priv(dev);
1802 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1803 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1804 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1815 struct de4x5_private *lp = netdev_priv(dev);
1836 lp->state = CLOSED;
1851 struct de4x5_private *lp = netdev_priv(dev);
1854 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1856 return &lp->stats;
1862 struct de4x5_private *lp = netdev_priv(dev);
1867 lp->pktStats.bins[i]++;
1873 lp->pktStats.broadcast++;
1875 lp->pktStats.multicast++;
1878 lp->pktStats.unicast++;
1881 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1882 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1883 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1898 struct de4x5_private *lp = netdev_priv(dev);
1899 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1900 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1902 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1903 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1904 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1905 lp->tx_skb[lp->tx_new] = skb;
1906 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1909 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1919 struct de4x5_private *lp = netdev_priv(dev);
1923 if (lp->state == OPEN) {
1931 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1934 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1949 struct de4x5_private *lp = netdev_priv(dev);
1964 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1976 lp->setup_frame[byte] |= bit;
2003 struct de4x5_private *lp;
2021 lp = netdev_priv(dev);
2024 lp->cfrv = (u_short) inl(PCI_CFRV);
2053 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2055 lp->chipset = device;
2056 lp->bus = EISA;
2128 struct de4x5_private *lp = netdev_priv(dev);
2140 lp->device = PCI_SLOT(this_dev->devfn);
2141 lp->bus_num = pb;
2148 lp->chipset = device;
2164 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2171 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2203 struct de4x5_private *lp;
2229 lp = netdev_priv(dev);
2230 lp->bus = PCI;
2231 lp->bus_num = 0;
2234 if (lp->bus_num != pb) {
2235 lp->bus_num = pb;
2240 lp->cfrv = pdev->revision;
2243 lp->device = dev_num;
2244 lp->bus_num = pb;
2248 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2250 lp->chipset = device;
2361 struct de4x5_private *lp = netdev_priv(dev);
2366 lp->c_media = AUTO; /* Bogus last media */
2368 lp->media = INIT;
2369 lp->tcount = 0;
2371 de4x5_ast(&lp->timer);
2373 return lp->media;
2391 struct de4x5_private *lp = netdev_priv(dev);
2396 switch (lp->media) {
2399 lp->tx_enable = false;
2400 lp->timeout = -1;
2402 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2403 lp->media = TP;
2404 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2405 lp->media = BNC_AUI;
2406 } else if (lp->autosense == EXT_SIA) {
2407 lp->media = EXT_SIA;
2409 lp->media = NC;
2411 lp->local_state = 0;
2447 if (lp->media != lp->c_media) {
2449 lp->c_media = lp->media;
2451 lp->media = INIT;
2452 lp->tx_enable = false;
2464 struct de4x5_private *lp = netdev_priv(dev);
2468 switch (lp->local_state) {
2471 lp->local_state++;
2476 if (!lp->tx_enable) {
2481 if (linkBad && (lp->autosense == AUTO)) {
2482 lp->local_state = 0;
2483 lp->media = next_state;
2488 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2489 lp->media = suspect_state;
2503 struct de4x5_private *lp = netdev_priv(dev);
2507 switch (lp->local_state) {
2509 if (lp->linkOK) {
2510 lp->media = prev_state;
2512 lp->local_state++;
2522 lp->local_state--;
2523 lp->media = prev_state;
2525 lp->media = INIT;
2526 lp->tcount++;
2545 struct de4x5_private *lp = netdev_priv(dev);
2550 switch (lp->media) {
2553 lp->tx_enable = false;
2554 lp->timeout = -1;
2556 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2557 lp->media = TP; /* On chip auto negotiation is broken */
2558 } else if (lp->autosense == TP) {
2559 lp->media = TP;
2560 } else if (lp->autosense == BNC) {
2561 lp->media = BNC;
2562 } else if (lp->autosense == AUI) {
2563 lp->media = AUI;
2565 lp->media = NC;
2567 lp->local_state = 0;
2572 if (lp->timeout < 0) {
2583 lp->media = ANS;
2585 lp->media = AUI;
2592 if (!lp->tx_enable) {
2599 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2600 lp->media = TP;
2603 lp->local_state = 1;
2607 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2608 lp->media = ANS_SUSPECT;
2618 if (!lp->tx_enable) {
2619 if (lp->timeout < 0) {
2629 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2631 lp->media = AUI; /* Non selected port activity */
2633 lp->media = BNC;
2637 lp->local_state = 1;
2641 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2642 lp->media = TP_SUSPECT;
2652 if (!lp->tx_enable) {
2653 if (lp->timeout < 0) {
2663 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2664 lp->media = BNC;
2667 lp->local_state = 1;
2671 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2672 lp->media = AUI_SUSPECT;
2682 switch (lp->local_state) {
2684 if (lp->timeout < 0) {
2694 lp->local_state++; /* Ensure media connected */
2700 if (!lp->tx_enable) {
2705 lp->local_state = 0;
2706 lp->media = NC;
2711 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2712 lp->media = BNC_SUSPECT;
2727 if (lp->media != lp->c_media) {
2729 lp->c_media = lp->media;
2731 lp->media = INIT;
2732 lp->tx_enable = false;
2747 struct de4x5_private *lp = netdev_priv(dev);
2752 switch(lp->media) {
2754 if (lp->timeout < 0) {
2756 lp->tx_enable = false;
2757 lp->linkOK = 0;
2763 if (lp->useSROM) {
2765 lp->tcount++;
2768 srom_exec(dev, lp->phy[lp->active].gep);
2769 if (lp->infoblock_media == ANS) {
2770 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2771 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2774 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2776 if (lp->autosense == _100Mb) {
2777 lp->media = _100Mb;
2778 } else if (lp->autosense == _10Mb) {
2779 lp->media = _10Mb;
2780 } else if ((lp->autosense == AUTO) &&
2783 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2784 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2785 lp->media = ANS;
2786 } else if (lp->autosense == AUTO) {
2787 lp->media = SPD_DET;
2789 lp->media = _100Mb;
2791 lp->media = NC;
2794 lp->local_state = 0;
2800 switch (lp->local_state) {
2802 if (lp->timeout < 0) {
2803 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2810 lp->local_state = 0;
2811 lp->media = SPD_DET;
2813 lp->local_state++;
2823 lp->media = SPD_DET;
2824 lp->local_state = 0;
2826 lp->tmp = MII_SR_ASSC;
2827 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2828 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2832 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2833 lp->media = _100Mb;
2835 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2837 lp->media = _10Mb;
2848 if (lp->timeout < 0) {
2849 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2857 lp->media = _100Mb;
2858 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2859 lp->media = _10Mb;
2861 lp->media = NC;
2869 if (!lp->tx_enable) {
2873 if (!lp->linkOK && (lp->autosense == AUTO)) {
2874 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2875 lp->media = INIT;
2876 lp->tcount++;
2887 if (!lp->tx_enable) {
2891 if (!lp->linkOK && (lp->autosense == AUTO)) {
2892 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2893 lp->media = INIT;
2894 lp->tcount++;
2902 if (lp->media != lp->c_media) {
2904 lp->c_media = lp->media;
2906 lp->media = INIT;
2907 lp->tx_enable = false;
2931 struct de4x5_private *lp = netdev_priv(dev);
2936 switch (lp->media) {
2938 if (lp->timeout < 0) {
2940 lp->tx_enable = false;
2941 lp->linkOK = 0;
2942 lp->timeout = -1;
2944 if (lp->params.autosense & ~AUTO) {
2946 if (lp->media != lp->params.autosense) {
2947 lp->tcount++;
2948 lp->media = INIT;
2951 lp->media = INIT;
2957 if (lp->autosense == _100Mb) {
2958 lp->media = _100Mb;
2959 } else if (lp->autosense == _10Mb) {
2960 lp->media = _10Mb;
2961 } else if (lp->autosense == TP) {
2962 lp->media = TP;
2963 } else if (lp->autosense == BNC) {
2964 lp->media = BNC;
2965 } else if (lp->autosense == AUI) {
2966 lp->media = AUI;
2968 lp->media = SPD_DET;
2969 if ((lp->infoblock_media == ANS) &&
2972 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2973 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2974 lp->media = ANS;
2977 lp->local_state = 0;
2983 switch (lp->local_state) {
2985 if (lp->timeout < 0) {
2986 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2993 lp->local_state = 0;
2994 lp->media = SPD_DET;
2996 lp->local_state++;
3007 lp->media = SPD_DET;
3008 lp->local_state = 0;
3010 lp->tmp = MII_SR_ASSC;
3011 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3012 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3016 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3017 lp->media = _100Mb;
3019 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3020 lp->media = _10Mb;
3031 if (!lp->tx_enable) {
3032 if (lp->timeout < 0) {
3042 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3043 lp->media = BNC;
3046 lp->local_state = 1;
3050 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3051 lp->media = AUI_SUSPECT;
3061 switch (lp->local_state) {
3063 if (lp->timeout < 0) {
3073 lp->local_state++; /* Ensure media connected */
3079 if (!lp->tx_enable) {
3084 lp->local_state = 0;
3085 lp->tcount++;
3086 lp->media = INIT;
3091 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3092 lp->media = BNC_SUSPECT;
3105 lp->tcount++;
3106 lp->media = INIT;
3109 if (lp->media == _100Mb) {
3111 lp->media = SPD_DET;
3116 lp->media = SPD_DET;
3120 if (lp->media == ANS) { /* Do MII parallel detection */
3122 lp->media = _100Mb;
3124 lp->media = _10Mb;
3127 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3128 (((lp->media == _10Mb) || (lp->media == TP) ||
3129 (lp->media == BNC) || (lp->media == AUI)) &&
3133 lp->tcount++;
3134 lp->media = INIT;
3140 if (!lp->tx_enable) {
3144 if (!lp->linkOK && (lp->autosense == AUTO)) {
3145 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3146 lp->media = INIT;
3147 lp->tcount++;
3156 if (!lp->tx_enable) {
3160 if (!lp->linkOK && (lp->autosense == AUTO)) {
3161 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3162 lp->media = INIT;
3163 lp->tcount++;
3171 lp->tcount++;
3172 printk("Huh?: media:%02x\n", lp->media);
3173 lp->media = INIT;
3183 struct de4x5_private *lp = netdev_priv(dev);
3185 return lp->infoleaf_fn(dev);
3196 struct de4x5_private *lp = netdev_priv(dev);
3198 lp->fdx = false;
3199 if (lp->infoblock_media == lp->media)
3202 switch(lp->infoblock_media) {
3204 if (!lp->params.fdx) return -1;
3205 lp->fdx = true;
3209 if (lp->params.fdx && !lp->fdx) return -1;
3210 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3211 lp->media = _10Mb;
3213 lp->media = TP;
3218 lp->media = BNC;
3222 lp->media = AUI;
3226 if (!lp->params.fdx) return -1;
3227 lp->fdx = true;
3231 if (lp->params.fdx && !lp->fdx) return -1;
3232 lp->media = _100Mb;
3236 lp->media = _100Mb;
3240 if (!lp->params.fdx) return -1;
3241 lp->fdx = true;
3245 if (lp->params.fdx && !lp->fdx) return -1;
3246 lp->media = _100Mb;
3250 lp->media = ANS;
3251 lp->fdx = lp->params.fdx;
3256 lp->infoblock_media);
3266 struct de4x5_private *lp = netdev_priv(dev);
3270 if (lp->media != lp->c_media) {
3272 lp->c_media = lp->media; /* Stop scrolling media messages */
3275 spin_lock_irqsave(&lp->lock, flags);
3278 lp->tx_enable = true;
3279 spin_unlock_irqrestore(&lp->lock, flags);
3293 struct de4x5_private *lp = netdev_priv(dev);
3297 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3298 if (lp->timeout < 0) {
3299 if (lp->useSROM) {
3300 if (lp->phy[lp->active].rst) {
3301 srom_exec(dev, lp->phy[lp->active].rst);
3302 srom_exec(dev, lp->phy[lp->active].rst);
3303 } else if (lp->rst) { /* Type 5 infoblock reset */
3304 srom_exec(dev, lp->rst);
3305 srom_exec(dev, lp->rst);
3310 if (lp->useMII) {
3311 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3314 if (lp->useMII) {
3317 } else if (lp->chipset == DC21140) {
3327 struct de4x5_private *lp = netdev_priv(dev);
3331 if (lp->timeout < 0) {
3332 lp->timeout = msec/100;
3333 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3345 if ((lp->chipset == DC21041) || lp->useSROM) {
3353 if (!(sts & irqs) && --lp->timeout) {
3356 lp->timeout = -1;
3365 struct de4x5_private *lp = netdev_priv(dev);
3369 if (lp->timeout < 0) {
3370 lp->timeout = msec/100;
3375 if (sisr && --lp->timeout) {
3378 lp->timeout = -1;
3394 struct de4x5_private *lp = netdev_priv(dev);
3395 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3397 if (lp->timeout < 0) {
3400 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3404 lp->timeout = msec/SAMPLE_INTERVAL;
3408 if (lp->phy[lp->active].id || lp->useSROM) {
3413 if (!(gep & ret) && --lp->timeout) {
3416 lp->timeout = -1;
3425 struct de4x5_private *lp = netdev_priv(dev);
3427 if (lp->timeout < 0) {
3428 lp->timeout = 1;
3431 if (lp->timeout--) {
3434 lp->timeout = -1;
3447 struct de4x5_private *lp = netdev_priv(dev);
3451 if (lp->timeout < 0) {
3452 lp->timeout = msec/100;
3455 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3458 if (test && --lp->timeout) {
3461 lp->timeout = -1;
3470 struct de4x5_private *lp = netdev_priv(dev);
3474 if (lp->useMII) {
3475 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3476 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3477 spd &= lp->phy[lp->active].spd.mask;
3478 } else if (!lp->useSROM) { /* de500-xa */
3481 if ((lp->ibn == 2) || !lp->asBitValid)
3482 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3484 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3485 (lp->linkOK & ~lp->asBitValid);
3494 struct de4x5_private *lp = netdev_priv(dev);
3497 if (lp->useMII) {
3499 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3500 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3501 } else if (!lp->useSROM) { /* de500-xa */
3504 if ((lp->ibn == 2) || !lp->asBitValid)
3505 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3507 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3508 (lp->linkOK & ~lp->asBitValid);
3515 struct de4x5_private *lp = netdev_priv(dev);
3518 if (lp->useMII) {
3520 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3521 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3522 } else if (!lp->useSROM) { /* de500-xa */
3525 if ((lp->ibn == 2) || !lp->asBitValid)
3526 return ((lp->chipset & ~0x00ff) == DC2114x) ?
3530 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3531 (lp->linkOK & ~lp->asBitValid);
3538 struct de4x5_private *lp = netdev_priv(dev);
3541 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3542 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3543 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3557 struct de4x5_private *lp = netdev_priv(dev);
3561 if (lp->timeout < 0) {
3562 lp->timeout = msec/100;
3564 lp->tmp = lp->tx_new; /* Remember the ring position */
3565 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3566 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
3573 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3574 (--lp->timeout)) {
3578 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3579 lp->timeout) {
3584 lp->timeout = -1;
3598 struct de4x5_private *lp = netdev_priv(dev);
3611 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3613 ret = lp->rx_skb[index];
3614 lp->rx_skb[index] = p;
3623 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3629 if (index < lp->rx_old) { /* Wrapped buffer */
3630 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3631 skb_put_data(p, lp->rx_bufs + lp->rx_old * RX_BUFF_SZ, tlen);
3632 skb_put_data(p, lp->rx_bufs, len - tlen);
3634 skb_put_data(p, lp->rx_bufs + lp->rx_old * RX_BUFF_SZ, len);
3644 struct de4x5_private *lp = netdev_priv(dev);
3647 for (i=0; i<lp->rxRingSize; i++) {
3648 if ((u_long) lp->rx_skb[i] > 1) {
3649 dev_kfree_skb(lp->rx_skb[i]);
3651 lp->rx_ring[i].status = 0;
3652 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3659 struct de4x5_private *lp = netdev_priv(dev);
3662 for (i=0; i<lp->txRingSize; i++) {
3663 if (lp->tx_skb[i])
3664 de4x5_free_tx_buff(lp, i);
3665 lp->tx_ring[i].status = 0;
3669 __skb_queue_purge(&lp->cache.queue);
3682 struct de4x5_private *lp = netdev_priv(dev);
3686 if (!lp->cache.save_cnt) {
3693 lp->cache.save_cnt++;
3701 struct de4x5_private *lp = netdev_priv(dev);
3706 if (lp->cache.save_cnt) {
3708 outl(lp->dma_rings, DE4X5_RRBA);
3709 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3712 lp->rx_new = lp->rx_old = 0;
3713 lp->tx_new = lp->tx_old = 0;
3715 for (i = 0; i < lp->rxRingSize; i++) {
3716 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3719 for (i = 0; i < lp->txRingSize; i++) {
3720 lp->tx_ring[i].status = cpu_to_le32(0);
3724 lp->cache.save_cnt--;
3732 struct de4x5_private *lp = netdev_priv(dev);
3737 lp->cache.csr0 = inl(DE4X5_BMR);
3738 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3739 lp->cache.csr7 = inl(DE4X5_IMR);
3743 outl(lp->cache.csr0, DE4X5_BMR);
3744 outl(lp->cache.csr6, DE4X5_OMR);
3745 outl(lp->cache.csr7, DE4X5_IMR);
3746 if (lp->chipset == DC21140) {
3747 gep_wr(lp->cache.gepc, dev);
3748 gep_wr(lp->cache.gep, dev);
3750 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3751 lp->cache.csr15);
3760 struct de4x5_private *lp = netdev_priv(dev);
3762 __skb_queue_tail(&lp->cache.queue, skb);
3768 struct de4x5_private *lp = netdev_priv(dev);
3770 __skb_queue_head(&lp->cache.queue, skb);
3776 struct de4x5_private *lp = netdev_priv(dev);
3778 return __skb_dequeue(&lp->cache.queue);
3788 struct de4x5_private *lp = netdev_priv(dev);
3792 if (lp->timeout < 0) {
3793 lp->timeout = msec/100;
3804 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3807 lp->timeout = -1;
3816 struct de4x5_private *lp = netdev_priv(dev);
3835 struct de4x5_private *lp = netdev_priv(dev);
3839 if (lp->useSROM) {
3840 if (lp->ibn == 3) {
3841 srom_exec(dev, lp->phy[lp->active].rst);
3842 srom_exec(dev, lp->phy[lp->active].gep);
3846 csr15 = lp->cache.csr15;
3847 csr14 = lp->cache.csr14;
3848 csr13 = lp->cache.csr13;
3849 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3850 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3906 PCI_signature(char *name, struct de4x5_private *lp)
3910 if (lp->chipset == DC21040) {
3914 int tmp = *((char *)&lp->srom + 19) * 3;
3915 strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3925 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3926 ((lp->chipset == DC21041) ? "DC21041" :
3927 ((lp->chipset == DC21140) ? "DC21140" :
3928 ((lp->chipset == DC21142) ? "DC21142" :
3929 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3932 if (lp->chipset != DC21041) {
3933 lp->useSROM = true; /* card is not recognisably DEC */
3935 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3936 lp->useSROM = true;
3952 struct de4x5_private *lp = netdev_priv(dev);
3954 if (lp->chipset == DC21040) {
3955 if (lp->bus == EISA) {
3962 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
3973 p = (__le16 *)&lp->srom;
3978 de4x5_dbg_srom(&lp->srom);
4031 struct de4x5_private *lp = netdev_priv(dev);
4033 broken = de4x5_bad_srom(lp);
4039 if (lp->bus == PCI) {
4040 if (lp->chipset == DC21040) {
4048 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4049 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4051 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4052 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4065 if (lp->bus == PCI) {
4066 if (lp->chipset == DC21040) {
4111 de4x5_bad_srom(struct de4x5_private *lp)
4116 if (!memcmp(&lp->srom, &enet_det[i], 3) &&
4117 !memcmp((char *)&lp->srom+0x10, &enet_det[i], 3)) {
4133 struct de4x5_private *lp = netdev_priv(dev);
4137 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4138 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4139 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4140 lp->useSROM = true;
4152 struct de4x5_private *lp = netdev_priv(dev);
4157 if ((lp->chipset == last.chipset) &&
4158 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4165 if (!an_exception(lp)) {
4172 last.chipset = lp->chipset;
4173 last.bus = lp->bus_num;
4185 an_exception(struct de4x5_private *lp)
4187 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4188 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4295 struct de4x5_private *lp = netdev_priv(dev);
4301 if (lp->chipset == infoleaf_array[i].chipset) break;
4304 lp->useSROM = false;
4310 lp->infoleaf_fn = infoleaf_array[i].fn;
4313 count = *((u_char *)&lp->srom + 19);
4314 p = (u_char *)&lp->srom + 26;
4318 if (lp->device == *p) break;
4321 lp->useSROM = false;
4323 dev->name, lp->device);
4328 lp->infoleaf_offset = get_unaligned_le16(p + 1);
4343 struct de4x5_private *lp = netdev_priv(dev);
4344 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4348 if (lp->chipset == DC21140) {
4349 lp->cache.gepc = (*p++ | GEP_CTRL);
4350 gep_wr(lp->cache.gepc, dev);
4386 struct de4x5_private *lp = netdev_priv(dev);
4391 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4393 if (lp->chipset != DC21140) RESET_SIA;
4396 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4401 if (lp->chipset != DC21140) {
4402 outl(lp->cache.csr14, DE4X5_STRR);
4403 outl(lp->cache.csr13, DE4X5_SICR);
4421 struct de4x5_private *lp = netdev_priv(dev);
4423 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4430 lp->cache.gepc = (*p++ | GEP_CTRL);
4442 if (lp->tcount == count) {
4443 lp->media = NC;
4444 if (lp->media != lp->c_media) {
4446 lp->c_media = lp->media;
4448 lp->media = INIT;
4449 lp->tcount = 0;
4450 lp->tx_enable = false;
4459 struct de4x5_private *lp = netdev_priv(dev);
4461 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4477 if (lp->tcount == count) {
4478 lp->media = NC;
4479 if (lp->media != lp->c_media) {
4481 lp->c_media = lp->media;
4483 lp->media = INIT;
4484 lp->tcount = 0;
4485 lp->tx_enable = false;
4494 struct de4x5_private *lp = netdev_priv(dev);
4496 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4511 if (lp->tcount == count) {
4512 lp->media = NC;
4513 if (lp->media != lp->c_media) {
4515 lp->c_media = lp->media;
4517 lp->media = INIT;
4518 lp->tcount = 0;
4519 lp->tx_enable = false;
4532 struct de4x5_private *lp = netdev_priv(dev);
4536 if (--count > lp->tcount) {
4544 if ((lp->media == INIT) && (lp->timeout < 0)) {
4545 lp->ibn = COMPACT;
4546 lp->active = 0;
4547 gep_wr(lp->cache.gepc, dev);
4548 lp->infoblock_media = (*p++) & COMPACT_MC;
4549 lp->cache.gep = *p++;
4553 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4554 lp->defMedium = (flags & 0x40) ? -1 : 0;
4555 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4556 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4557 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4558 lp->useMII = false;
4572 struct de4x5_private *lp = netdev_priv(dev);
4576 if (--count > lp->tcount) {
4584 if ((lp->media == INIT) && (lp->timeout < 0)) {
4585 lp->ibn = 0;
4586 lp->active = 0;
4587 gep_wr(lp->cache.gepc, dev);
4589 lp->infoblock_media = (*p++) & BLOCK0_MC;
4590 lp->cache.gep = *p++;
4594 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4595 lp->defMedium = (flags & 0x40) ? -1 : 0;
4596 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4597 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4598 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4599 lp->useMII = false;
4612 struct de4x5_private *lp = netdev_priv(dev);
4616 if (--count > lp->tcount) {
4625 if (lp->state == INITIALISED) {
4626 lp->ibn = 1;
4627 lp->active = *p++;
4628 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4629 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4630 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4631 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4632 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4633 lp->phy[lp->active].ttm = get_unaligned_le16(p);
4635 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4636 lp->ibn = 1;
4637 lp->active = *p;
4638 lp->infoblock_csr6 = OMR_MII_100;
4639 lp->useMII = true;
4640 lp->infoblock_media = ANS;
4651 struct de4x5_private *lp = netdev_priv(dev);
4655 if (--count > lp->tcount) {
4663 if ((lp->media == INIT) && (lp->timeout < 0)) {
4664 lp->ibn = 2;
4665 lp->active = 0;
4667 lp->infoblock_media = (*p) & MEDIA_CODE;
4670 lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4671 lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4672 lp->cache.csr15 = get_unaligned_le16(p); p += 2;
4674 lp->cache.csr13 = CSR13;
4675 lp->cache.csr14 = CSR14;
4676 lp->cache.csr15 = CSR15;
4678 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4679 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16);
4680 lp->infoblock_csr6 = OMR_SIA;
4681 lp->useMII = false;
4692 struct de4x5_private *lp = netdev_priv(dev);
4696 if (--count > lp->tcount) {
4705 if (lp->state == INITIALISED) {
4706 lp->ibn = 3;
4707 lp->active = *p++;
4708 if (MOTO_SROM_BUG) lp->active = 0;
4709 /* if (MOTO_SROM_BUG) statement indicates lp->active could
4710 * be 8 (i.e. the size of array lp->phy) */
4711 if (WARN_ON(lp->active >= ARRAY_SIZE(lp->phy)))
4713 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4714 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4715 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4716 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4717 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4718 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
4719 lp->phy[lp->active].mci = *p;
4721 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4722 lp->ibn = 3;
4723 lp->active = *p;
4724 if (MOTO_SROM_BUG) lp->active = 0;
4725 lp->infoblock_csr6 = OMR_MII_100;
4726 lp->useMII = true;
4727 lp->infoblock_media = ANS;
4738 struct de4x5_private *lp = netdev_priv(dev);
4742 if (--count > lp->tcount) {
4750 if ((lp->media == INIT) && (lp->timeout < 0)) {
4751 lp->ibn = 4;
4752 lp->active = 0;
4754 lp->infoblock_media = (*p++) & MEDIA_CODE;
4755 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4756 lp->cache.csr14 = CSR14;
4757 lp->cache.csr15 = CSR15;
4758 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4759 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4763 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4764 lp->defMedium = (flags & 0x40) ? -1 : 0;
4765 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4766 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4767 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4768 lp->useMII = false;
4783 struct de4x5_private *lp = netdev_priv(dev);
4787 if (--count > lp->tcount) {
4796 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4798 lp->rst = p;
4799 srom_exec(dev, lp->rst);
4973 struct de4x5_private *lp = netdev_priv(dev);
4978 lp->active = 0;
4979 lp->useMII = true;
4982 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
4983 lp->phy[lp->active].addr = i;
4990 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
4992 memcpy((char *)&lp->phy[k],
4994 lp->phy[k].addr = i;
4995 lp->mii_cnt++;
4996 lp->active++;
5003 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
5005 lp->phy[k].addr = i;
5006 lp->phy[k].id = id;
5007 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5008 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5009 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5010 lp->mii_cnt++;
5011 lp->active++;
5024 lp->active = 0;
5025 if (lp->phy[0].id) { /* Reset the PHY devices */
5026 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/
5027 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5028 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5033 if (!lp->mii_cnt) lp->useMII = false;
5035 return lp->mii_cnt;
5041 struct de4x5_private *lp = netdev_priv(dev);
5043 char *pa = lp->setup_frame;
5047 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5050 if (lp->setup_f == HASH_PERF) {
5051 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5055 *(lp->setup_frame + (DE4X5_HASH_TABLE_LEN >> 3) - 3) = 0x80;
5073 struct de4x5_private *lp = netdev_priv(dev);
5074 del_timer_sync(&lp->timer);
5080 struct de4x5_private *lp = netdev_priv(dev);
5089 omr |= lp->infoblock_csr6;
5097 if (lp->chipset == DC21140) {
5098 gep_wr(lp->cache.gepc, dev);
5099 gep_wr(lp->cache.gep, dev);
5100 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5101 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5116 struct de4x5_private *lp = netdev_priv(dev);
5119 if (lp->chipset == DC21140) {
5121 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5122 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5129 struct de4x5_private *lp = netdev_priv(dev);
5132 if (lp->chipset == DC21140) {
5134 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5144 struct de4x5_private *lp = netdev_priv(dev);
5147 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5149 if(lp->bus == EISA) {
5166 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5188 struct de4x5_private *lp = netdev_priv(dev);
5191 lp->params.fdx = false;
5192 lp->params.autosense = AUTO;
5201 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = true;
5205 lp->params.autosense = TP_NW;
5207 lp->params.autosense = TP;
5209 lp->params.autosense = BNC;
5211 lp->params.autosense = BNC;
5213 lp->params.autosense = AUI;
5215 lp->params.autosense = _10Mb;
5217 lp->params.autosense = _100Mb;
5219 lp->params.autosense = AUTO;
5229 struct de4x5_private *lp = netdev_priv(dev);
5236 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5238 for (i=0;i<lp->rxRingSize-1;i++){
5240 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5243 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5245 for (i=0;i<lp->txRingSize-1;i++){
5247 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5250 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5252 for (i=0;i<lp->rxRingSize-1;i++){
5254 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5257 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5259 for (i=0;i<lp->txRingSize-1;i++){
5261 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5264 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5266 (short)lp->rxRingSize,
5267 (short)lp->txRingSize);
5274 struct de4x5_private *lp = netdev_priv(dev);
5278 printk("\nMII device address: %d\n", lp->phy[k].addr);
5279 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5280 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5281 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5282 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5283 if (lp->phy[k].id != BROADCOM_T4) {
5284 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5285 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5287 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5288 if (lp->phy[k].id != BROADCOM_T4) {
5289 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5290 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5292 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5300 struct de4x5_private *lp = netdev_priv(dev);
5302 if (lp->media != lp->c_media) {
5305 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5306 (lp->media == TP ? "TP" :
5307 (lp->media == ANS ? "TP/Nway" :
5308 (lp->media == BNC ? "BNC" :
5309 (lp->media == AUI ? "AUI" :
5310 (lp->media == BNC_AUI ? "BNC/AUI" :
5311 (lp->media == EXT_SIA ? "EXT SIA" :
5312 (lp->media == _100Mb ? "100Mb/s" :
5313 (lp->media == _10Mb ? "10Mb/s" :
5315 ))))))))), (lp->fdx?" full duplex.":"."));
5317 lp->c_media = lp->media;
5370 struct de4x5_private *lp = netdev_priv(dev);
5402 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5404 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
5425 spin_lock_irqsave(&lp->lock, flags);
5426 memcpy(&statbuf, &lp->pktStats, ioc->len);
5427 spin_unlock_irqrestore(&lp->lock, flags);
5434 spin_lock_irqsave(&lp->lock, flags);
5435 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5436 spin_unlock_irqrestore(&lp->lock, flags);
5473 tmp.addr[j++] = lp->rxRingSize;
5474 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5475 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5477 for (i=0;i<lp->rxRingSize-1;i++){
5479 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5482 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5483 for (i=0;i<lp->txRingSize-1;i++){
5485 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5488 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5490 for (i=0;i<lp->rxRingSize-1;i++){
5492 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5495 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5496 for (i=0;i<lp->txRingSize-1;i++){
5498 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5501 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5503 for (i=0;i<lp->rxRingSize;i++){
5504 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5506 for (i=0;i<lp->txRingSize;i++){
5507 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5518 tmp.lval[j>>2] = lp->chipset; j+=4;
5519 if (lp->chipset == DC21140) {
5527 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5528 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5529 tmp.lval[j>>2] = lp->active; j+=4;
5530 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5531 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5532 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5533 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5534 if (lp->phy[lp->active].id != BROADCOM_T4) {
5535 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5536 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5538 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5539 if (lp->phy[lp->active].id != BROADCOM_T4) {
5540 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5541 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5543 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5547 tmp.addr[j++] = lp->txRingSize;