Lines Matching defs:tmp
824 int tmp; /* Temporary global per card */
2774 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2826 lp->tmp = MII_SR_ASSC;
2849 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2858 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
3010 lp->tmp = MII_SR_ASSC;
3564 lp->tmp = lp->tx_new; /* Remember the ring position */
3573 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3578 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3603 u_long i=0, tmp;
3608 tmp = virt_to_bus(p->data);
3609 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3611 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3914 int tmp = *((char *)&lp->srom + 19) * 3;
3915 strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3961 u_short tmp;
3964 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
3965 j += tmp; /* for check for 0:0:0:0:0:0 or ff:ff:ff:ff:ff:ff */
3966 *p = cpu_to_le16(tmp);
3975 tmp = srom_rd(aprom_addr, i);
3976 *p++ = cpu_to_le16(tmp);
4029 int broken, i, k, tmp, status = 0;
4041 while ((tmp = inl(DE4X5_APROM)) < 0);
4042 k += (u_char) tmp;
4043 dev->dev_addr[i++] = (u_char) tmp;
4044 while ((tmp = inl(DE4X5_APROM)) < 0);
4045 k += (u_short) (tmp << 8);
4046 dev->dev_addr[i++] = (u_char) tmp;
4055 k += (u_char) (tmp = inb(EISA_APROM));
4056 dev->dev_addr[i++] = (u_char) tmp;
4057 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4058 dev->dev_addr[i++] = (u_char) tmp;
4067 while ((tmp = inl(DE4X5_APROM)) < 0);
4068 chksum = (u_char) tmp;
4069 while ((tmp = inl(DE4X5_APROM)) < 0);
4070 chksum |= (u_short) (tmp << 8);
4153 int i, tmp;
4155 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4156 if ((tmp == 0) || (tmp == 0x5fa)) {
4245 s32 tmp;
4249 tmp = getfrom_srom(addr);
4252 word = (word << 1) | ((tmp >> 3) & 0x01);
4284 s32 tmp;
4286 tmp = inl(addr);
4289 return tmp;
4839 s32 tmp = 0;
4842 tmp <<= 1;
4843 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4846 return tmp;
4886 int i, tmp = 0;
4889 tmp <<= 1;
4890 tmp |= (data & 1);
4894 return tmp;
5379 } tmp;
5386 tmp.addr[i] = dev->dev_addr[i];
5388 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5393 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5398 dev->dev_addr[i] = tmp.addr[i];
5440 tmp.addr[0] = inl(DE4X5_OMR);
5441 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5446 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5447 outl(tmp.addr[0], DE4X5_OMR);
5452 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5453 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5454 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5455 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5456 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5457 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5458 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5459 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5461 if (copy_to_user(ioc->data, tmp.lval, ioc->len))
5469 tmp.addr[j++] = dev->irq;
5471 tmp.addr[j++] = dev->dev_addr[i];
5473 tmp.addr[j++] = lp->rxRingSize;
5474 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5475 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5479 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5482 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5485 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5488 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5492 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5495 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5498 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5501 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5504 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5507 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5510 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5511 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5512 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5513 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5514 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5515 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5516 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5517 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5518 tmp.lval[j>>2] = lp->chipset; j+=4;
5520 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5522 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5523 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5524 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5525 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5527 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5529 tmp.lval[j>>2] = lp->active; j+=4;
5530 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5531 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5532 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5533 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5535 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5536 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5538 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5540 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5541 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5543 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5547 tmp.addr[j++] = lp->txRingSize;
5548 tmp.addr[j++] = netif_queue_stopped(dev);
5551 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;