Lines Matching refs:wrl
182 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
190 wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
213 wrl(ep, REG_MIIDATA, data);
214 wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
318 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
361 wrl(ep, REG_TXDENQ, 1);
432 wrl(ep, REG_INTEN, REG_INTEN_TX);
537 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
549 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
553 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
557 wrl(ep, REG_RXDQBADD, addr);
558 wrl(ep, REG_RXDCURADD, addr);
563 wrl(ep, REG_RXSTSQBADD, addr);
564 wrl(ep, REG_RXSTSQCURADD, addr);
569 wrl(ep, REG_TXDQBADD, addr);
570 wrl(ep, REG_TXDQCURADD, addr);
575 wrl(ep, REG_TXSTSQBADD, addr);
576 wrl(ep, REG_TXSTSQCURADD, addr);
579 wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
580 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
581 wrl(ep, REG_GIINTMSK, 0);
594 wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
595 wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
603 wrl(ep, REG_AFP, 0);
605 wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
607 wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
608 wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
618 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
660 wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
674 wrl(ep, REG_GIINTMSK, 0);