Lines Matching refs:adapter
50 * @adapter: the adapter performing the operation
61 static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
65 u32 val = readl(adapter->regs + reg) & mask;
81 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
85 writel(addr, adapter->regs + A_TPI_ADDR);
86 writel(value, adapter->regs + A_TPI_WR_DATA);
87 writel(F_TPIWR, adapter->regs + A_TPI_CSR);
89 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
93 adapter->name, addr);
97 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
101 spin_lock(&adapter->tpi_lock);
102 ret = __t1_tpi_write(adapter, addr, value);
103 spin_unlock(&adapter->tpi_lock);
110 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
114 writel(addr, adapter->regs + A_TPI_ADDR);
115 writel(0, adapter->regs + A_TPI_CSR);
117 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
121 adapter->name, addr);
123 *valp = readl(adapter->regs + A_TPI_RD_DATA);
127 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
131 spin_lock(&adapter->tpi_lock);
132 ret = __t1_tpi_read(adapter, addr, valp);
133 spin_unlock(&adapter->tpi_lock);
140 static void t1_tpi_par(adapter_t *adapter, u32 value)
142 writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
150 void t1_link_changed(adapter_t *adapter, int port_id)
153 struct cphy *phy = adapter->port[port_id].phy;
154 struct link_config *lc = &adapter->port[port_id].link_config;
165 struct cmac *mac = adapter->port[port_id].mac;
170 t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
173 static int t1_pci_intr_handler(adapter_t *adapter)
177 pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
180 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
182 t1_fatal_err(adapter); /* PCI errors are fatal */
193 static int fpga_phy_intr_handler(adapter_t *adapter)
196 u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
198 for_each_port(adapter, p)
200 struct cphy *phy = adapter->port[p].phy;
204 t1_link_changed(adapter, p);
206 writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
213 static int fpga_slow_intr(adapter_t *adapter)
215 u32 cause = readl(adapter->regs + A_PL_CAUSE);
219 t1_sge_intr_error_handler(adapter->sge);
222 fpga_phy_intr_handler(adapter);
229 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
232 writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
235 t1_pci_intr_handler(adapter);
239 writel(cause, adapter->regs + A_PL_CAUSE);
248 static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
255 __t1_tpi_read(adapter, mi1_reg, &val);
261 pr_alert("%s: MDIO operation timed out\n", adapter->name);
268 static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
276 t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
286 struct adapter *adapter = dev->ml_priv;
290 spin_lock(&adapter->tpi_lock);
291 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
292 __t1_tpi_write(adapter,
294 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
295 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
296 spin_unlock(&adapter->tpi_lock);
303 struct adapter *adapter = dev->ml_priv;
306 spin_lock(&adapter->tpi_lock);
307 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
308 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
309 __t1_tpi_write(adapter,
311 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
312 spin_unlock(&adapter->tpi_lock);
328 struct adapter *adapter = dev->ml_priv;
332 spin_lock(&adapter->tpi_lock);
335 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
336 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
337 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
339 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
342 __t1_tpi_write(adapter,
344 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
347 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
348 spin_unlock(&adapter->tpi_lock);
355 struct adapter *adapter = dev->ml_priv;
358 spin_lock(&adapter->tpi_lock);
361 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
362 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
363 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
365 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
368 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
369 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
370 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
371 spin_unlock(&adapter->tpi_lock);
562 int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)
571 pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
574 pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
579 adapter->name, addr);
582 pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);
587 static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
592 ret = t1_seeprom_read(adapter, addr,
601 static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
605 if (t1_eeprom_vpd_get(adapter, &vpd))
631 (mac->adapter->params.nports < 2)))
667 int t1_elmer0_ext_intr_handler(adapter_t *adapter)
673 t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
675 switch (board_info(adapter)->board) {
682 for_each_port(adapter, i) {
687 phy = adapter->port[i].phy;
690 t1_link_changed(adapter, i);
696 phy = adapter->port[0].phy;
699 t1_link_changed(adapter, 0);
710 for_each_port(adapter, p) {
711 phy = adapter->port[p].phy;
714 t1_link_changed(adapter, p);
723 phy = adapter->port[0].phy;
726 t1_link_changed(adapter, 0);
731 if (netif_msg_intr(adapter))
732 dev_dbg(&adapter->pdev->dev,
735 struct cmac *mac = adapter->port[0].mac;
742 t1_tpi_read(adapter,
744 if (netif_msg_link(adapter))
745 dev_info(&adapter->pdev->dev, "XPAK %s\n",
750 t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
755 void t1_interrupts_enable(adapter_t *adapter)
759 adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
761 t1_sge_intr_enable(adapter->sge);
762 t1_tp_intr_enable(adapter->tp);
763 if (adapter->espi) {
764 adapter->slow_intr_mask |= F_PL_INTR_ESPI;
765 t1_espi_intr_enable(adapter->espi);
769 for_each_port(adapter, i) {
770 adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
771 adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
775 if (t1_is_asic(adapter)) {
776 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
779 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
782 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
784 writel(pl_intr, adapter->regs + A_PL_ENABLE);
789 void t1_interrupts_disable(adapter_t* adapter)
793 t1_sge_intr_disable(adapter->sge);
794 t1_tp_intr_disable(adapter->tp);
795 if (adapter->espi)
796 t1_espi_intr_disable(adapter->espi);
799 for_each_port(adapter, i) {
800 adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
801 adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
805 if (t1_is_asic(adapter))
806 writel(0, adapter->regs + A_PL_ENABLE);
809 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
811 adapter->slow_intr_mask = 0;
815 void t1_interrupts_clear(adapter_t* adapter)
819 t1_sge_intr_clear(adapter->sge);
820 t1_tp_intr_clear(adapter->tp);
821 if (adapter->espi)
822 t1_espi_intr_clear(adapter->espi);
825 for_each_port(adapter, i) {
826 adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
827 adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
831 if (t1_is_asic(adapter)) {
832 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
835 adapter->regs + A_PL_CAUSE);
839 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
845 static int asic_slow_intr(adapter_t *adapter)
847 u32 cause = readl(adapter->regs + A_PL_CAUSE);
849 cause &= adapter->slow_intr_mask;
853 t1_sge_intr_error_handler(adapter->sge);
855 t1_tp_intr_handler(adapter->tp);
857 t1_espi_intr_handler(adapter->espi);
859 t1_pci_intr_handler(adapter);
861 t1_elmer0_ext_intr(adapter);
864 writel(cause, adapter->regs + A_PL_CAUSE);
865 readl(adapter->regs + A_PL_CAUSE); /* flush writes */
869 int t1_slow_intr_handler(adapter_t *adapter)
872 if (!t1_is_asic(adapter))
873 return fpga_slow_intr(adapter);
875 return asic_slow_intr(adapter);
879 static void power_sequence_xpak(adapter_t* adapter)
885 t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
888 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
890 t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
894 int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
902 u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
920 static int board_init(adapter_t *adapter, const struct board_info *bi)
927 t1_tpi_par(adapter, 0xf);
928 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
931 t1_tpi_par(adapter, 0xf);
932 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
937 power_sequence_xpak(adapter);
945 t1_tpi_par(adapter, 0xf);
946 t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
950 t1_tpi_par(adapter, 0xf);
951 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
962 int t1_init_hw_modules(adapter_t *adapter)
965 const struct board_info *bi = board_info(adapter);
968 u32 val = readl(adapter->regs + A_MC4_CFG);
970 writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
972 adapter->regs + A_MC5_CONFIG);
975 if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
979 if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
982 err = t1_sge_configure(adapter->sge, &adapter->params.sge);
994 static void get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
999 pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
1008 void t1_free_sw_modules(adapter_t *adapter)
1012 for_each_port(adapter, i) {
1013 struct cmac *mac = adapter->port[i].mac;
1014 struct cphy *phy = adapter->port[i].phy;
1022 if (adapter->sge)
1023 t1_sge_destroy(adapter->sge);
1024 if (adapter->tp)
1025 t1_tp_destroy(adapter->tp);
1026 if (adapter->espi)
1027 t1_espi_destroy(adapter->espi);
1051 int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi)
1055 adapter->params.brd_info = bi;
1056 adapter->params.nports = bi->port_number;
1057 adapter->params.stats_update_period = bi->gmac->stats_update_period;
1059 adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
1060 if (!adapter->sge) {
1062 adapter->name);
1066 if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
1068 adapter->name);
1072 adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
1073 if (!adapter->tp) {
1075 adapter->name);
1079 board_init(adapter, bi);
1080 bi->mdio_ops->init(adapter, bi);
1082 bi->gphy->reset(adapter);
1084 bi->gmac->reset(adapter);
1086 for_each_port(adapter, i) {
1091 adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev,
1093 if (!adapter->port[i].phy) {
1095 adapter->name, i);
1099 adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
1102 adapter->name, i);
1110 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
1112 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
1114 adapter->port[i].dev->name);
1117 memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
1118 init_link_config(&adapter->port[i].link_config, bi);
1121 get_pci_mode(adapter, &adapter->params.pci);
1122 t1_interrupts_clear(adapter);
1126 t1_free_sw_modules(adapter);