Lines Matching refs:cmac
94 static int pmread(struct cmac *cmac, u32 reg, u32 * data32)
96 t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
100 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)
102 t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
107 static int pm3393_reset(struct cmac *cmac)
120 static int pm3393_interrupt_enable(struct cmac *cmac)
126 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);
127 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);
128 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);
129 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);
132 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
133 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
134 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
135 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
137 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);
138 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);
139 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);
140 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);
141 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);
142 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);
143 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);
144 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);
145 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);
150 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,
154 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);
156 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);
160 static int pm3393_interrupt_disable(struct cmac *cmac)
165 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);
166 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);
167 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);
168 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);
169 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
170 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
171 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
172 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
173 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);
174 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);
175 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);
176 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);
177 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);
178 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);
179 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);
180 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);
181 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);
184 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);
187 t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);
189 t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
199 static int pm3393_interrupt_clear(struct cmac *cmac)
208 pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);
209 pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);
210 pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);
211 pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);
212 pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);
213 pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);
214 pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);
215 pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);
216 pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);
217 pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);
218 pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);
219 pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,
221 pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);
222 pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);
226 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);
230 t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);
232 t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);
236 pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);
238 writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);
244 static int pm3393_interrupt_handler(struct cmac *cmac)
249 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
251 if (netif_msg_intr(cmac->adapter))
252 dev_dbg(&cmac->adapter->pdev->dev, "PM3393 intr cause 0x%x\n",
256 pm3393_interrupt_clear(cmac);
261 static int pm3393_enable(struct cmac *cmac, int which)
264 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,
270 if (cmac->instance->fc & PAUSE_RX)
272 if (cmac->instance->fc & PAUSE_TX)
274 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);
277 cmac->instance->enabled |= which;
281 static int pm3393_enable_port(struct cmac *cmac, int which)
284 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
287 memset(&cmac->stats, 0, sizeof(struct cmac_statistics));
289 pm3393_enable(cmac, which);
296 t1_link_changed(cmac->adapter, 0);
300 static int pm3393_disable(struct cmac *cmac, int which)
303 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);
305 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);
313 cmac->instance->enabled &= ~which;
317 static int pm3393_loopback_enable(struct cmac *cmac)
322 static int pm3393_loopback_disable(struct cmac *cmac)
327 static int pm3393_set_mtu(struct cmac *cmac, int mtu)
329 int enabled = cmac->instance->enabled;
335 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
337 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);
338 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);
341 pm3393_enable(cmac, enabled);
345 static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
347 int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
352 pm3393_disable(cmac, MAC_DIRECTION_RX);
354 pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);
357 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2,
366 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);
367 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);
368 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);
369 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);
382 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
383 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);
384 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);
385 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);
389 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);
392 pm3393_enable(cmac, MAC_DIRECTION_RX);
397 static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,
405 *fc = cmac->instance->fc;
409 static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
419 if (fc != cmac->instance->fc) {
420 cmac->instance->fc = (u8) fc;
421 if (cmac->instance->enabled & MAC_DIRECTION_TX)
422 pm3393_enable(cmac, MAC_DIRECTION_TX);
442 static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
493 static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])
495 memcpy(mac_addr, cmac->instance->mac_addr, ETH_ALEN);
499 static int pm3393_macaddress_set(struct cmac *cmac, u8 ma[6])
501 u32 val, lo, mid, hi, enabled = cmac->instance->enabled;
522 memcpy(cmac->instance->mac_addr, ma, ETH_ALEN);
530 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
533 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);
534 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);
535 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);
538 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);
539 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);
540 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);
546 pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);
548 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
550 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);
551 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);
552 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);
555 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
558 pm3393_enable(cmac, enabled);
562 static void pm3393_destroy(struct cmac *cmac)
564 kfree(cmac);
587 static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)
589 struct cmac *cmac;
591 cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);
592 if (!cmac)
595 cmac->ops = &pm3393_ops;
596 cmac->instance = (cmac_instance *) (cmac + 1);
597 cmac->adapter = adapter;
598 cmac->instance->fc = PAUSE_TX | PAUSE_RX;
681 return cmac;