Lines Matching defs:adapter
44 adapter_t *adapter;
60 static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
70 adapter->regs + A_ESPI_CMD_ADDR);
71 writel(0, adapter->regs + A_ESPI_GOSTAT);
74 busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY;
78 pr_err("%s: TRICN write timed out\n", adapter->name);
83 static int tricn_init(adapter_t *adapter)
87 if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) {
88 pr_err("%s: ESPI clock not ready\n", adapter->name);
92 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET);
95 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);
96 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);
97 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);
100 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);
102 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);
104 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
105 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1);
106 tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1);
107 tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1);
108 tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80);
109 tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1);
112 adapter->regs + A_ESPI_RX_RESET);
119 u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
128 enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK;
129 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE);
130 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
135 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
136 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);
137 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE);
142 u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
144 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE);
145 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
150 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
169 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
176 if (status && t1_is_T1B(espi->adapter))
178 writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
187 static void espi_setup_for_pm3393(adapter_t *adapter)
189 u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
191 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
192 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1);
193 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
194 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3);
195 writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
196 writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
197 writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH);
198 writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
199 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG);
202 static void espi_setup_for_vsc7321(adapter_t *adapter)
204 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
205 writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1);
206 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
207 writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
208 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
209 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
210 writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG);
212 writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
218 static void espi_setup_for_ixf1010(adapter_t *adapter, int nports)
220 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
222 if (is_T2(adapter)) {
223 writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
224 writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
226 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
227 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
230 writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
231 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
233 writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG);
240 adapter_t *adapter = espi->adapter;
243 writel(0, adapter->regs + A_ESPI_TRAIN);
245 if (is_T2(adapter)) {
248 V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL);
250 adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
252 writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
255 espi_setup_for_pm3393(adapter);
257 espi_setup_for_vsc7321(adapter);
260 espi_setup_for_ixf1010(adapter, nports);
265 adapter->regs + A_ESPI_FIFO_STATUS_ENABLE);
267 if (is_T2(adapter)) {
268 tricn_init(adapter);
273 espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL);
276 if (adapter->params.nports == 1)
278 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
290 struct peespi *t1_espi_create(adapter_t *adapter)
295 espi->adapter = adapter;
300 void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
302 struct peespi *espi = adapter->espi;
304 if (!is_T2(adapter))
309 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
314 u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
316 struct peespi *espi = adapter->espi;
319 if (!is_T2(adapter))
331 adapter->regs + A_ESPI_MISC_CONTROL);
332 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
333 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
335 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
345 int t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait)
347 struct peespi *espi = adapter->espi;
348 u8 i, nport = (u8)adapter->params.nports;
359 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
364 adapter->regs + A_ESPI_MISC_CONTROL);
366 *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
369 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);