Lines Matching refs:tp
91 #define tg3_flag(tp, flag) \
92 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
93 #define tg3_flag_set(tp, flag) \
94 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define tg3_flag_clear(tp, flag) \
96 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
129 #define TG3_MAX_MTU(tp) \
130 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
136 #define TG3_RX_STD_RING_SIZE(tp) \
137 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
140 #define TG3_RX_JMB_RING_SIZE(tp) \
141 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
145 /* Do not place this n-ring entries value into the tp struct itself,
155 #define TG3_RX_STD_RING_BYTES(tp) \
156 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
157 #define TG3_RX_JMB_RING_BYTES(tp) \
158 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
159 #define TG3_RX_RCB_RING_BYTES(tp) \
160 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
175 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
176 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
178 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
179 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
194 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
196 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
200 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
202 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
212 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
213 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
469 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
471 writel(val, tp->regs + off);
474 static u32 tg3_read32(struct tg3 *tp, u32 off)
476 return readl(tp->regs + off);
479 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
481 writel(val, tp->aperegs + off);
484 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
486 return readl(tp->aperegs + off);
489 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
493 spin_lock_irqsave(&tp->indirect_lock, flags);
494 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
495 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
496 spin_unlock_irqrestore(&tp->indirect_lock, flags);
499 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
501 writel(val, tp->regs + off);
502 readl(tp->regs + off);
505 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
510 spin_lock_irqsave(&tp->indirect_lock, flags);
511 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
512 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
513 spin_unlock_irqrestore(&tp->indirect_lock, flags);
517 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
522 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
527 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
532 spin_lock_irqsave(&tp->indirect_lock, flags);
533 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
534 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
535 spin_unlock_irqrestore(&tp->indirect_lock, flags);
542 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
543 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
547 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
552 spin_lock_irqsave(&tp->indirect_lock, flags);
553 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
554 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
555 spin_unlock_irqrestore(&tp->indirect_lock, flags);
564 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
566 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
568 tp->write32(tp, off, val);
571 tg3_write32(tp, off, val);
574 tp->read32(tp, off);
583 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
585 tp->write32_mbox(tp, off, val);
586 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
587 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
588 !tg3_flag(tp, ICH_WORKAROUND)))
589 tp->read32_mbox(tp, off);
592 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
594 void __iomem *mbox = tp->regs + off;
596 if (tg3_flag(tp, TXD_MBOX_HWBUG))
598 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
599 tg3_flag(tp, FLUSH_POSTED_WRITES))
603 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
605 return readl(tp->regs + off + GRCMBOX_BASE);
608 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
610 writel(val, tp->regs + off + GRCMBOX_BASE);
613 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
614 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
615 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
616 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
617 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
619 #define tw32(reg, val) tp->write32(tp, reg, val)
620 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
621 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
622 #define tr32(reg) tp->read32(tp, reg)
624 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
628 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
632 spin_lock_irqsave(&tp->indirect_lock, flags);
633 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
634 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
635 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
638 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
646 spin_unlock_irqrestore(&tp->indirect_lock, flags);
649 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
653 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
659 spin_lock_irqsave(&tp->indirect_lock, flags);
660 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
661 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
662 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
665 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
673 spin_unlock_irqrestore(&tp->indirect_lock, flags);
676 static void tg3_ape_lock_init(struct tg3 *tp)
681 if (tg3_asic_rev(tp) == ASIC_REV_5761)
696 if (!tp->pci_fn)
699 bit = 1 << tp->pci_fn;
701 tg3_ape_write32(tp, regbase + 4 * i, bit);
706 static int tg3_ape_lock(struct tg3 *tp, int locknum)
712 if (!tg3_flag(tp, ENABLE_APE))
717 if (tg3_asic_rev(tp) == ASIC_REV_5761)
722 if (!tp->pci_fn)
725 bit = 1 << tp->pci_fn;
737 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
747 tg3_ape_write32(tp, req + off, bit);
751 status = tg3_ape_read32(tp, gnt + off);
754 if (pci_channel_offline(tp->pdev))
762 tg3_ape_write32(tp, gnt + off, bit);
769 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
773 if (!tg3_flag(tp, ENABLE_APE))
778 if (tg3_asic_rev(tp) == ASIC_REV_5761)
783 if (!tp->pci_fn)
786 bit = 1 << tp->pci_fn;
798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
806 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
828 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
833 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
844 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
850 if (!tg3_flag(tp, APE_HAS_NCSI))
853 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
857 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
861 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
864 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
873 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
878 err = tg3_ape_event_lock(tp, 1000);
885 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
887 tg3_ape_write32(tp, bufoff, base_off);
888 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
890 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
891 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
895 if (tg3_ape_wait_for_event(tp, 30000))
899 u32 val = tg3_ape_read32(tp, msgoff + i);
909 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
914 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
918 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
923 err = tg3_ape_event_lock(tp, 20000);
927 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
930 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
931 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
936 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
941 if (!tg3_flag(tp, ENABLE_APE))
946 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
947 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
949 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
951 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
952 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
953 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
955 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
957 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
963 if (device_may_wakeup(&tp->pdev->dev) &&
964 tg3_flag(tp, WOL_ENABLE)) {
965 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
971 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
981 tg3_ape_send_event(tp, event);
984 static void tg3_send_ape_heartbeat(struct tg3 *tp,
988 if (!tg3_flag(tp, ENABLE_APE) ||
989 time_before(jiffies, tp->ape_hb_jiffies + interval))
992 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
993 tp->ape_hb_jiffies = jiffies;
996 static void tg3_disable_ints(struct tg3 *tp)
1001 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
1002 for (i = 0; i < tp->irq_max; i++)
1003 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1006 static void tg3_enable_ints(struct tg3 *tp)
1010 tp->irq_sync = 0;
1014 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1016 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1017 for (i = 0; i < tp->irq_cnt; i++) {
1018 struct tg3_napi *tnapi = &tp->napi[i];
1021 if (tg3_flag(tp, 1SHOT_MSI))
1024 tp->coal_now |= tnapi->coal_now;
1028 if (!tg3_flag(tp, TAGGED_STATUS) &&
1029 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1030 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1032 tw32(HOSTCC_MODE, tp->coal_now);
1034 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1039 struct tg3 *tp = tnapi->tp;
1044 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1068 struct tg3 *tp = tnapi->tp;
1076 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1077 tw32(HOSTCC_MODE, tp->coalesce_mode |
1081 static void tg3_switch_clocks(struct tg3 *tp)
1086 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1095 tp->pci_clock_ctrl = clock_ctrl;
1097 if (tg3_flag(tp, 5705_PLUS)) {
1116 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1123 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1125 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1129 tg3_ape_lock(tp, tp->phy_ape_lock);
1160 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1161 tw32_f(MAC_MI_MODE, tp->mi_mode);
1165 tg3_ape_unlock(tp, tp->phy_ape_lock);
1170 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1172 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1175 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1182 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1186 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1188 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1192 tg3_ape_lock(tp, tp->phy_ape_lock);
1219 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1220 tw32_f(MAC_MI_MODE, tp->mi_mode);
1224 tg3_ape_unlock(tp, tp->phy_ape_lock);
1229 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1231 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1234 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1238 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1242 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1246 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1251 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1257 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1261 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1265 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1269 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1274 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1280 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1284 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1286 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1291 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1295 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1297 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1302 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1306 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1310 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1315 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1320 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1323 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1328 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1338 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1344 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1346 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1350 static int tg3_bmcr_reset(struct tg3 *tp)
1359 err = tg3_writephy(tp, MII_BMCR, phy_control);
1365 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1383 struct tg3 *tp = bp->priv;
1386 spin_lock_bh(&tp->lock);
1388 if (__tg3_readphy(tp, mii_id, reg, &val))
1391 spin_unlock_bh(&tp->lock);
1398 struct tg3 *tp = bp->priv;
1401 spin_lock_bh(&tp->lock);
1403 if (__tg3_writephy(tp, mii_id, reg, val))
1406 spin_unlock_bh(&tp->lock);
1411 static void tg3_mdio_config_5785(struct tg3 *tp)
1416 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1447 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1460 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1461 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1463 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1478 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1479 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1484 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1492 static void tg3_mdio_start(struct tg3 *tp)
1494 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1495 tw32_f(MAC_MI_MODE, tp->mi_mode);
1498 if (tg3_flag(tp, MDIOBUS_INITED) &&
1499 tg3_asic_rev(tp) == ASIC_REV_5785)
1500 tg3_mdio_config_5785(tp);
1503 static int tg3_mdio_init(struct tg3 *tp)
1509 if (tg3_flag(tp, 5717_PLUS)) {
1512 tp->phy_addr = tp->pci_fn + 1;
1514 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1520 tp->phy_addr += 7;
1521 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1524 addr = ssb_gige_get_phyaddr(tp->pdev);
1527 tp->phy_addr = addr;
1529 tp->phy_addr = TG3_PHY_MII_ADDR;
1531 tg3_mdio_start(tp);
1533 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1536 tp->mdio_bus = mdiobus_alloc();
1537 if (tp->mdio_bus == NULL)
1540 tp->mdio_bus->name = "tg3 mdio bus";
1541 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1542 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1543 tp->mdio_bus->priv = tp;
1544 tp->mdio_bus->parent = &tp->pdev->dev;
1545 tp->mdio_bus->read = &tg3_mdio_read;
1546 tp->mdio_bus->write = &tg3_mdio_write;
1547 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1554 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1555 tg3_bmcr_reset(tp);
1557 i = mdiobus_register(tp->mdio_bus);
1559 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1560 mdiobus_free(tp->mdio_bus);
1564 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1567 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1568 mdiobus_unregister(tp->mdio_bus);
1569 mdiobus_free(tp->mdio_bus);
1584 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1586 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1588 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1598 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1602 tg3_flag_set(tp, MDIOBUS_INITED);
1604 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1605 tg3_mdio_config_5785(tp);
1610 static void tg3_mdio_fini(struct tg3 *tp)
1612 if (tg3_flag(tp, MDIOBUS_INITED)) {
1613 tg3_flag_clear(tp, MDIOBUS_INITED);
1614 mdiobus_unregister(tp->mdio_bus);
1615 mdiobus_free(tp->mdio_bus);
1619 /* tp->lock is held. */
1620 static inline void tg3_generate_fw_event(struct tg3 *tp)
1628 tp->last_event_jiffies = jiffies;
1633 /* tp->lock is held. */
1634 static void tg3_wait_for_event_ack(struct tg3 *tp)
1641 time_remain = (long)(tp->last_event_jiffies + 1 +
1656 if (pci_channel_offline(tp->pdev))
1663 /* tp->lock is held. */
1664 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1669 if (!tg3_readphy(tp, MII_BMCR, ®))
1671 if (!tg3_readphy(tp, MII_BMSR, ®))
1676 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1678 if (!tg3_readphy(tp, MII_LPA, ®))
1683 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1684 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1686 if (!tg3_readphy(tp, MII_STAT1000, ®))
1691 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1698 /* tp->lock is held. */
1699 static void tg3_ump_link_report(struct tg3 *tp)
1703 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1706 tg3_phy_gather_ump_data(tp, data);
1708 tg3_wait_for_event_ack(tp);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1713 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1714 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1717 tg3_generate_fw_event(tp);
1720 /* tp->lock is held. */
1721 static void tg3_stop_fw(struct tg3 *tp)
1723 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1725 tg3_wait_for_event_ack(tp);
1727 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1729 tg3_generate_fw_event(tp);
1732 tg3_wait_for_event_ack(tp);
1736 /* tp->lock is held. */
1737 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1739 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1742 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1745 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1750 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1755 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1765 /* tp->lock is held. */
1766 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1768 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1771 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1776 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1786 /* tp->lock is held. */
1787 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1789 if (tg3_flag(tp, ENABLE_ASF)) {
1792 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1797 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1802 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1812 static int tg3_poll_fw(struct tg3 *tp)
1817 if (tg3_flag(tp, NO_FWARE_REPORTED))
1820 if (tg3_flag(tp, IS_SSB_CORE)) {
1825 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1830 if (pci_channel_offline(tp->pdev))
1840 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1843 if (pci_channel_offline(tp->pdev)) {
1844 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1845 tg3_flag_set(tp, NO_FWARE_REPORTED);
1846 netdev_info(tp->dev, "No firmware running\n");
1860 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1861 tg3_flag_set(tp, NO_FWARE_REPORTED);
1863 netdev_info(tp->dev, "No firmware running\n");
1866 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1876 static void tg3_link_report(struct tg3 *tp)
1878 if (!netif_carrier_ok(tp->dev)) {
1879 netif_info(tp, link, tp->dev, "Link is down\n");
1880 tg3_ump_link_report(tp);
1881 } else if (netif_msg_link(tp)) {
1882 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1883 (tp->link_config.active_speed == SPEED_1000 ?
1885 (tp->link_config.active_speed == SPEED_100 ?
1887 (tp->link_config.active_duplex == DUPLEX_FULL ?
1890 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1891 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1893 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1896 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1897 netdev_info(tp->dev, "EEE is %s\n",
1898 tp->setlpicnt ? "enabled" : "disabled");
1900 tg3_ump_link_report(tp);
1903 tp->link_up = netif_carrier_ok(tp->dev);
1966 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1970 u32 old_rx_mode = tp->rx_mode;
1971 u32 old_tx_mode = tp->tx_mode;
1973 if (tg3_flag(tp, USE_PHYLIB))
1974 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg;
1976 autoneg = tp->link_config.autoneg;
1978 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1979 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1984 flowctrl = tp->link_config.flowctrl;
1986 tp->link_config.active_flowctrl = flowctrl;
1989 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1991 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1993 if (old_rx_mode != tp->rx_mode)
1994 tw32_f(MAC_RX_MODE, tp->rx_mode);
1997 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1999 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
2001 if (old_tx_mode != tp->tx_mode)
2002 tw32_f(MAC_TX_MODE, tp->tx_mode);
2009 struct tg3 *tp = netdev_priv(dev);
2010 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2012 spin_lock_bh(&tp->lock);
2014 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2017 oldflowctrl = tp->link_config.active_flowctrl;
2026 tg3_asic_rev(tp) != ASIC_REV_5785)
2035 tp->link_config.flowctrl);
2043 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2047 if (mac_mode != tp->mac_mode) {
2048 tp->mac_mode = mac_mode;
2049 tw32_f(MAC_MODE, tp->mac_mode);
2053 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2073 if (phydev->link != tp->old_link ||
2074 phydev->speed != tp->link_config.active_speed ||
2075 phydev->duplex != tp->link_config.active_duplex ||
2076 oldflowctrl != tp->link_config.active_flowctrl)
2079 tp->old_link = phydev->link;
2080 tp->link_config.active_speed = phydev->speed;
2081 tp->link_config.active_duplex = phydev->duplex;
2083 spin_unlock_bh(&tp->lock);
2086 tg3_link_report(tp);
2089 static int tg3_phy_init(struct tg3 *tp)
2093 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2097 tg3_bmcr_reset(tp);
2099 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2102 phydev = phy_connect(tp->dev, phydev_name(phydev),
2105 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2113 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2124 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2128 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2135 static void tg3_phy_start(struct tg3 *tp)
2139 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2142 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2144 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2145 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2146 phydev->speed = tp->link_config.speed;
2147 phydev->duplex = tp->link_config.duplex;
2148 phydev->autoneg = tp->link_config.autoneg;
2150 phydev->advertising, tp->link_config.advertising);
2158 static void tg3_phy_stop(struct tg3 *tp)
2160 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2163 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2166 static void tg3_phy_fini(struct tg3 *tp)
2168 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2169 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2170 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2174 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2179 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2182 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2184 err = tg3_phy_auxctl_write(tp,
2191 err = tg3_phy_auxctl_read(tp,
2197 err = tg3_phy_auxctl_write(tp,
2204 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2208 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2211 tg3_writephy(tp, MII_TG3_FET_TEST,
2213 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2218 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2220 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2224 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2228 if (!tg3_flag(tp, 5705_PLUS) ||
2229 (tg3_flag(tp, 5717_PLUS) &&
2230 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2233 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2234 tg3_phy_fet_toggle_apd(tp, enable);
2242 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2245 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2252 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2255 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2259 if (!tg3_flag(tp, 5705_PLUS) ||
2260 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2263 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2266 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2269 tg3_writephy(tp, MII_TG3_FET_TEST,
2271 if (!tg3_readphy(tp, reg, &phy)) {
2276 tg3_writephy(tp, reg, phy);
2278 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2283 ret = tg3_phy_auxctl_read(tp,
2290 tg3_phy_auxctl_write(tp,
2296 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2301 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2304 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2306 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2310 static void tg3_phy_apply_otp(struct tg3 *tp)
2314 if (!tp->phy_otp)
2317 otp = tp->phy_otp;
2319 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2324 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2328 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2332 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2335 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2338 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2342 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2344 tg3_phy_toggle_auxctl_smdsp(tp, false);
2347 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2350 struct ethtool_eee *dest = &tp->eee;
2352 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2358 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2369 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2374 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2387 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2391 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2394 tp->setlpicnt = 0;
2396 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2398 tp->link_config.active_duplex == DUPLEX_FULL &&
2399 (tp->link_config.active_speed == SPEED_100 ||
2400 tp->link_config.active_speed == SPEED_1000)) {
2403 if (tp->link_config.active_speed == SPEED_1000)
2410 tg3_eee_pull_config(tp, NULL);
2411 if (tp->eee.eee_active)
2412 tp->setlpicnt = 2;
2415 if (!tp->setlpicnt) {
2417 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2418 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2419 tg3_phy_toggle_auxctl_smdsp(tp, false);
2427 static void tg3_phy_eee_enable(struct tg3 *tp)
2431 if (tp->link_config.active_speed == SPEED_1000 &&
2432 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2433 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2434 tg3_flag(tp, 57765_CLASS)) &&
2435 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2438 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2439 tg3_phy_toggle_auxctl_smdsp(tp, false);
2446 static int tg3_wait_macro_done(struct tg3 *tp)
2453 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2464 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2477 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2479 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2482 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2485 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2486 if (tg3_wait_macro_done(tp)) {
2491 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2494 if (tg3_wait_macro_done(tp)) {
2499 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2500 if (tg3_wait_macro_done(tp)) {
2508 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2509 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2510 tg3_wait_macro_done(tp)) {
2518 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2519 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2520 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2530 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2537 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2539 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2541 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2542 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2543 if (tg3_wait_macro_done(tp))
2550 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2559 err = tg3_bmcr_reset(tp);
2566 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2570 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2573 tg3_writephy(tp, MII_BMCR,
2577 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2580 tg3_writephy(tp, MII_CTRL1000,
2583 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2588 tg3_phydsp_write(tp, 0x8005, 0x0800);
2590 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2595 err = tg3_phy_reset_chanpat(tp);
2599 tg3_phydsp_write(tp, 0x8005, 0x0000);
2601 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2602 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2604 tg3_phy_toggle_auxctl_smdsp(tp, false);
2606 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2608 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2613 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2618 static void tg3_carrier_off(struct tg3 *tp)
2620 netif_carrier_off(tp->dev);
2621 tp->link_up = false;
2624 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2626 if (tg3_flag(tp, ENABLE_ASF))
2627 netdev_warn(tp->dev,
2634 static int tg3_phy_reset(struct tg3 *tp)
2639 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2644 err = tg3_readphy(tp, MII_BMSR, &val);
2645 err |= tg3_readphy(tp, MII_BMSR, &val);
2649 if (netif_running(tp->dev) && tp->link_up) {
2650 netif_carrier_off(tp->dev);
2651 tg3_link_report(tp);
2654 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2655 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2656 tg3_asic_rev(tp) == ASIC_REV_5705) {
2657 err = tg3_phy_reset_5703_4_5(tp);
2664 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2665 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2672 err = tg3_bmcr_reset(tp);
2678 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2683 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2684 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2694 if (tg3_flag(tp, 5717_PLUS) &&
2695 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2698 tg3_phy_apply_otp(tp);
2700 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2701 tg3_phy_toggle_apd(tp, true);
2703 tg3_phy_toggle_apd(tp, false);
2706 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2707 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2708 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2709 tg3_phydsp_write(tp, 0x000a, 0x0323);
2710 tg3_phy_toggle_auxctl_smdsp(tp, false);
2713 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2714 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2715 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2718 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2719 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2720 tg3_phydsp_write(tp, 0x000a, 0x310b);
2721 tg3_phydsp_write(tp, 0x201f, 0x9506);
2722 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2723 tg3_phy_toggle_auxctl_smdsp(tp, false);
2725 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2726 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2727 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2728 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2729 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2730 tg3_writephy(tp, MII_TG3_TEST1,
2733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2735 tg3_phy_toggle_auxctl_smdsp(tp, false);
2741 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2743 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2744 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2746 err = tg3_phy_auxctl_read(tp,
2749 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2756 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2757 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2758 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2762 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2764 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2767 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2768 tg3_phydsp_write(tp, 0xffb, 0x4000);
2770 tg3_phy_toggle_automdix(tp, true);
2771 tg3_phy_set_wirespeed(tp);
2791 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2795 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2796 tg3_asic_rev(tp) == ASIC_REV_5719)
2797 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2801 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2805 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2806 tg3_asic_rev(tp) == ASIC_REV_5719)
2807 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2814 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2816 if (!tg3_flag(tp, IS_NIC))
2819 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2820 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2821 tg3_asic_rev(tp) == ASIC_REV_5720) {
2822 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2825 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2827 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2830 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2832 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2839 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2843 if (!tg3_flag(tp, IS_NIC) ||
2844 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2845 tg3_asic_rev(tp) == ASIC_REV_5701)
2848 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2863 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2865 if (!tg3_flag(tp, IS_NIC))
2868 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2869 tg3_asic_rev(tp) == ASIC_REV_5701) {
2870 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2877 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2878 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2885 tp->grc_local_ctrl;
2901 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2903 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2909 no_gpio2 = tp->nic_sram_data_cfg &
2922 tp->grc_local_ctrl | grc_local_ctrl,
2928 tp->grc_local_ctrl | grc_local_ctrl,
2934 tp->grc_local_ctrl | grc_local_ctrl,
2940 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2945 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2948 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2951 msg = tg3_set_function_status(tp, msg);
2957 tg3_pwrsrc_switch_to_vaux(tp);
2959 tg3_pwrsrc_die_with_vmain(tp);
2962 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2965 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2970 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2973 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2974 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2975 tg3_asic_rev(tp) == ASIC_REV_5720) {
2976 tg3_frob_aux_power_5717(tp, include_wol ?
2977 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2981 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2984 dev_peer = pci_get_drvdata(tp->pdev_peer);
2999 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
3000 tg3_flag(tp, ENABLE_ASF))
3004 tg3_pwrsrc_switch_to_vaux(tp);
3006 tg3_pwrsrc_die_with_vmain(tp);
3009 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3011 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3013 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3022 static bool tg3_phy_power_bug(struct tg3 *tp)
3024 switch (tg3_asic_rev(tp)) {
3029 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3033 if (!tp->pci_fn)
3038 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3039 !tp->pci_fn)
3047 static bool tg3_phy_led_bug(struct tg3 *tp)
3049 switch (tg3_asic_rev(tp)) {
3052 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3053 !tp->pci_fn)
3061 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3065 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3068 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3069 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3081 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3082 tg3_bmcr_reset(tp);
3087 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3089 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3092 tg3_writephy(tp, MII_ADVERTISE, 0);
3093 tg3_writephy(tp, MII_BMCR,
3096 tg3_writephy(tp, MII_TG3_FET_TEST,
3098 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3100 tg3_writephy(tp,
3104 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3108 if (!tg3_phy_led_bug(tp))
3109 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3115 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3121 if (tg3_phy_power_bug(tp))
3124 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3125 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3132 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3135 /* tp->lock is held. */
3136 static int tg3_nvram_lock(struct tg3 *tp)
3138 if (tg3_flag(tp, NVRAM)) {
3141 if (tp->nvram_lock_cnt == 0) {
3153 tp->nvram_lock_cnt++;
3158 /* tp->lock is held. */
3159 static void tg3_nvram_unlock(struct tg3 *tp)
3161 if (tg3_flag(tp, NVRAM)) {
3162 if (tp->nvram_lock_cnt > 0)
3163 tp->nvram_lock_cnt--;
3164 if (tp->nvram_lock_cnt == 0)
3169 /* tp->lock is held. */
3170 static void tg3_enable_nvram_access(struct tg3 *tp)
3172 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3179 /* tp->lock is held. */
3180 static void tg3_disable_nvram_access(struct tg3 *tp)
3182 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3189 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3231 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3250 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3252 if (tg3_flag(tp, NVRAM) &&
3253 tg3_flag(tp, NVRAM_BUFFERED) &&
3254 tg3_flag(tp, FLASH) &&
3255 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3256 (tp->nvram_jedecnum == JEDEC_ATMEL))
3258 addr = ((addr / tp->nvram_pagesize) <<
3260 (addr % tp->nvram_pagesize);
3265 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3267 if (tg3_flag(tp, NVRAM) &&
3268 tg3_flag(tp, NVRAM_BUFFERED) &&
3269 tg3_flag(tp, FLASH) &&
3270 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3271 (tp->nvram_jedecnum == JEDEC_ATMEL))
3274 tp->nvram_pagesize) +
3286 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3290 if (!tg3_flag(tp, NVRAM))
3291 return tg3_nvram_read_using_eeprom(tp, offset, val);
3293 offset = tg3_nvram_phys_addr(tp, offset);
3298 ret = tg3_nvram_lock(tp);
3302 tg3_enable_nvram_access(tp);
3305 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3311 tg3_disable_nvram_access(tp);
3313 tg3_nvram_unlock(tp);
3319 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3322 int res = tg3_nvram_read(tp, offset, &v);
3328 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3378 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3382 u32 pagesize = tp->nvram_pagesize;
3398 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3417 tg3_enable_nvram_access(tp);
3425 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3434 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3440 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3460 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3469 tg3_nvram_exec_cmd(tp, nvram_cmd);
3477 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3489 page_off = offset % tp->nvram_pagesize;
3491 phy_addr = tg3_nvram_phys_addr(tp, offset);
3497 if (page_off == (tp->nvram_pagesize - 4))
3504 !tg3_flag(tp, FLASH) ||
3505 !tg3_flag(tp, 57765_PLUS))
3508 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3509 !tg3_flag(tp, 5755_PLUS) &&
3510 (tp->nvram_jedecnum == JEDEC_ST) &&
3515 ret = tg3_nvram_exec_cmd(tp, cmd);
3519 if (!tg3_flag(tp, FLASH)) {
3524 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3532 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3536 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3537 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3542 if (!tg3_flag(tp, NVRAM)) {
3543 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3547 ret = tg3_nvram_lock(tp);
3551 tg3_enable_nvram_access(tp);
3552 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3558 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3559 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3562 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3569 tg3_disable_nvram_access(tp);
3570 tg3_nvram_unlock(tp);
3573 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3574 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3586 /* tp->lock is held. */
3587 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3597 if (pci_channel_offline(tp->pdev))
3604 /* tp->lock is held. */
3605 static int tg3_rxcpu_pause(struct tg3 *tp)
3607 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3616 /* tp->lock is held. */
3617 static int tg3_txcpu_pause(struct tg3 *tp)
3619 return tg3_pause_cpu(tp, TX_CPU_BASE);
3622 /* tp->lock is held. */
3623 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3629 /* tp->lock is held. */
3630 static void tg3_rxcpu_resume(struct tg3 *tp)
3632 tg3_resume_cpu(tp, RX_CPU_BASE);
3635 /* tp->lock is held. */
3636 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3640 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3642 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3649 rc = tg3_rxcpu_pause(tp);
3655 if (tg3_flag(tp, IS_SSB_CORE))
3658 rc = tg3_txcpu_pause(tp);
3662 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3668 if (tg3_flag(tp, NVRAM))
3673 static int tg3_fw_data_len(struct tg3 *tp,
3682 * tp->fw->size minus headers.
3692 if (tp->fw_len == 0xffffffff)
3695 fw_len = tp->fw->size;
3700 /* tp->lock is held. */
3701 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3707 int total_len = tp->fw->size;
3709 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3710 netdev_err(tp->dev,
3716 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3721 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3725 int lock_err = tg3_nvram_lock(tp);
3726 err = tg3_halt_cpu(tp, cpu_base);
3728 tg3_nvram_unlock(tp);
3733 write_op(tp, cpu_scratch_base + i, 0);
3747 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3748 write_op(tp, cpu_scratch_base +
3766 /* tp->lock is held. */
3767 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3787 /* tp->lock is held. */
3788 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3793 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3801 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3807 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3814 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3817 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3824 tg3_rxcpu_resume(tp);
3829 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3846 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3850 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3852 netdev_warn(tp->dev,
3860 /* tp->lock is held. */
3861 static void tg3_load_57766_firmware(struct tg3 *tp)
3865 if (!tg3_flag(tp, NO_NVRAM))
3868 if (tg3_validate_rxcpu_state(tp))
3871 if (!tp->fw)
3888 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3892 if (tg3_rxcpu_pause(tp))
3896 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3898 tg3_rxcpu_resume(tp);
3901 /* tp->lock is held. */
3902 static int tg3_load_tso_firmware(struct tg3 *tp)
3908 if (!tg3_flag(tp, FW_TSO))
3911 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3919 cpu_scratch_size = tp->fw_len;
3921 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3930 err = tg3_load_firmware_cpu(tp, cpu_base,
3937 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3940 netdev_err(tp->dev,
3947 tg3_resume_cpu(tp, cpu_base);
3951 /* tp->lock is held. */
3952 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3970 /* tp->lock is held. */
3971 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3979 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3982 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3983 tg3_asic_rev(tp) == ASIC_REV_5704) {
3985 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3988 addr_high = (tp->dev->dev_addr[0] +
3989 tp->dev->dev_addr[1] +
3990 tp->dev->dev_addr[2] +
3991 tp->dev->dev_addr[3] +
3992 tp->dev->dev_addr[4] +
3993 tp->dev->dev_addr[5]) &
3998 static void tg3_enable_register_access(struct tg3 *tp)
4004 pci_write_config_dword(tp->pdev,
4005 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4008 static int tg3_power_up(struct tg3 *tp)
4012 tg3_enable_register_access(tp);
4014 err = pci_set_power_state(tp->pdev, PCI_D0);
4017 tg3_pwrsrc_switch_to_vmain(tp);
4019 netdev_err(tp->dev, "Transition to D0 failed\n");
4027 static int tg3_power_down_prepare(struct tg3 *tp)
4032 tg3_enable_register_access(tp);
4035 if (tg3_flag(tp, CLKREQ_BUG))
4036 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4043 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4044 tg3_flag(tp, WOL_ENABLE);
4046 if (tg3_flag(tp, USE_PHYLIB)) {
4048 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4049 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4054 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
4056 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4058 tp->link_config.speed = phydev->speed;
4059 tp->link_config.duplex = phydev->duplex;
4060 tp->link_config.autoneg = phydev->autoneg;
4062 &tp->link_config.advertising,
4073 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4074 if (tg3_flag(tp, WOL_SPEED_100MB)) {
4102 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4103 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4105 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4106 tg3_setup_phy(tp, false);
4109 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4114 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4119 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4125 if (tg3_flag(tp, WOL_CAP))
4126 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4134 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4136 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4137 tg3_phy_auxctl_write(tp,
4145 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4147 else if (tp->phy_flags &
4149 if (tp->link_config.active_speed == SPEED_1000)
4156 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4157 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4158 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4160 if (tg3_5700_link_polarity(tp, speed))
4169 if (!tg3_flag(tp, 5750_PLUS))
4170 tw32(MAC_LED_CTRL, tp->led_ctrl);
4173 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4174 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4177 if (tg3_flag(tp, ENABLE_APE))
4189 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4190 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4191 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4194 base_val = tp->pci_clock_ctrl;
4200 } else if (tg3_flag(tp, 5780_CLASS) ||
4201 tg3_flag(tp, CPMU_PRESENT) ||
4202 tg3_asic_rev(tp) == ASIC_REV_5906) {
4204 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4207 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4208 tg3_asic_rev(tp) == ASIC_REV_5701) {
4213 } else if (tg3_flag(tp, 5705_PLUS)) {
4221 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4224 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4227 if (!tg3_flag(tp, 5705_PLUS)) {
4230 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4231 tg3_asic_rev(tp) == ASIC_REV_5701) {
4240 tp->pci_clock_ctrl | newbits3, 40);
4244 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4245 tg3_power_down_phy(tp, do_low_power);
4247 tg3_frob_aux_power(tp, true);
4250 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4251 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4252 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4257 if (!tg3_flag(tp, ENABLE_ASF)) {
4260 err = tg3_nvram_lock(tp);
4261 tg3_halt_cpu(tp, RX_CPU_BASE);
4263 tg3_nvram_unlock(tp);
4267 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4269 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4274 static void tg3_power_down(struct tg3 *tp)
4276 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4277 pci_set_power_state(tp->pdev, PCI_D3hot);
4280 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)
4314 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4327 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4336 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4340 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4343 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4344 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4347 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4352 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4358 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4370 if (!tp->eee.eee_enabled) {
4372 tp->eee.advertised = 0;
4374 tp->eee.advertised = advertise &
4379 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4383 switch (tg3_asic_rev(tp)) {
4393 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4397 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4398 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4402 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4411 static void tg3_phy_copper_begin(struct tg3 *tp)
4413 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4414 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4417 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4418 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4421 if (tg3_flag(tp, WOL_SPEED_100MB))
4424 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4425 if (!(tp->phy_flags &
4433 adv = tp->link_config.advertising;
4434 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4438 fc = tp->link_config.flowctrl;
4441 tg3_phy_autoneg_cfg(tp, adv, fc);
4443 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4444 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4452 tg3_writephy(tp, MII_BMCR,
4458 tp->link_config.active_speed = tp->link_config.speed;
4459 tp->link_config.active_duplex = tp->link_config.duplex;
4461 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4466 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4470 switch (tp->link_config.speed) {
4484 if (tp->link_config.duplex == DUPLEX_FULL)
4487 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4489 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4494 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4495 tg3_readphy(tp, MII_BMSR, &tmp))
4502 tg3_writephy(tp, MII_BMCR, bmcr);
4508 static int tg3_phy_pull_config(struct tg3 *tp)
4513 err = tg3_readphy(tp, MII_BMCR, &val);
4518 tp->link_config.autoneg = AUTONEG_DISABLE;
4519 tp->link_config.advertising = 0;
4520 tg3_flag_clear(tp, PAUSE_AUTONEG);
4526 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4529 tp->link_config.speed = SPEED_10;
4532 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4535 tp->link_config.speed = SPEED_100;
4538 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4539 tp->link_config.speed = SPEED_1000;
4548 tp->link_config.duplex = DUPLEX_FULL;
4550 tp->link_config.duplex = DUPLEX_HALF;
4552 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4558 tp->link_config.autoneg = AUTONEG_ENABLE;
4559 tp->link_config.advertising = ADVERTISED_Autoneg;
4560 tg3_flag_set(tp, PAUSE_AUTONEG);
4562 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4565 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4570 tp->link_config.advertising |= adv | ADVERTISED_TP;
4572 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4574 tp->link_config.advertising |= ADVERTISED_FIBRE;
4577 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4580 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4581 err = tg3_readphy(tp, MII_CTRL1000, &val);
4587 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4592 tp->link_config.flowctrl = adv;
4598 tp->link_config.advertising |= adv;
4605 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4611 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4613 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4614 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4615 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4616 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4617 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4624 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4628 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4631 tg3_eee_pull_config(tp, &eee);
4633 if (tp->eee.eee_enabled) {
4634 if (tp->eee.advertised != eee.advertised ||
4635 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4636 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4647 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4651 advertising = tp->link_config.advertising;
4655 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4656 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4660 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4666 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4671 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4675 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4676 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4691 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4695 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4698 if (tg3_readphy(tp, MII_STAT1000, &val))
4704 if (tg3_readphy(tp, MII_LPA, rmtadv))
4708 tp->link_config.rmt_adv = lpeth;
4713 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4715 if (curr_link_up != tp->link_up) {
4717 netif_carrier_on(tp->dev);
4719 netif_carrier_off(tp->dev);
4720 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4721 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4724 tg3_link_report(tp);
4731 static void tg3_clear_mac_status(struct tg3 *tp)
4743 static void tg3_setup_eee(struct tg3 *tp)
4749 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4758 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4762 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4765 if (tg3_flag(tp, ENABLE_APE))
4768 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4772 (tp->eee.tx_lpi_timer & 0xffff));
4779 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4788 tg3_clear_mac_status(tp);
4790 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4792 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4796 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4801 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4802 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4803 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4804 tp->link_up) {
4805 tg3_readphy(tp, MII_BMSR, &bmsr);
4806 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4811 tg3_phy_reset(tp);
4813 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4814 tg3_readphy(tp, MII_BMSR, &bmsr);
4815 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4816 !tg3_flag(tp, INIT_COMPLETE))
4820 err = tg3_init_5401phy_dsp(tp);
4824 tg3_readphy(tp, MII_BMSR, &bmsr);
4827 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4834 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4837 tp->link_config.active_speed == SPEED_1000) {
4838 err = tg3_phy_reset(tp);
4840 err = tg3_init_5401phy_dsp(tp);
4845 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4846 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4848 tg3_writephy(tp, 0x15, 0x0a75);
4849 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4850 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4851 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4855 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4856 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4858 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4859 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4860 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4861 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4863 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4864 tg3_asic_rev(tp) == ASIC_REV_5701) {
4865 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4866 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4869 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4875 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4876 tp->link_config.rmt_adv = 0;
4878 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4879 err = tg3_phy_auxctl_read(tp,
4883 tg3_phy_auxctl_write(tp,
4892 tg3_readphy(tp, MII_BMSR, &bmsr);
4893 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4902 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4905 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4910 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4916 tg3_readphy(tp, MII_BMCR, &bmcr);
4917 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4927 tp->link_config.active_speed = current_speed;
4928 tp->link_config.active_duplex = current_duplex;
4930 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4931 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4935 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4936 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4944 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4946 tg3_setup_eee(tp);
4947 tg3_phy_reset(tp);
4951 tp->link_config.speed == current_speed &&
4952 tp->link_config.duplex == current_duplex) {
4958 tp->link_config.active_duplex == DUPLEX_FULL) {
4961 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4969 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4970 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4972 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4977 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4978 tg3_phy_copper_begin(tp);
4980 if (tg3_flag(tp, ROBOSWITCH)) {
4985 tp->link_config.active_speed = current_speed;
4986 tp->link_config.active_duplex = current_duplex;
4989 tg3_readphy(tp, MII_BMSR, &bmsr);
4990 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4991 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4995 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4997 if (tp->link_config.active_speed == SPEED_100 ||
4998 tp->link_config.active_speed == SPEED_10)
4999 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5001 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5002 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
5003 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5005 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5010 if (tg3_flag(tp, RGMII_MODE)) {
5014 if (tp->link_config.active_speed == SPEED_10)
5016 else if (tp->link_config.active_speed == SPEED_100)
5019 else if (tp->link_config.active_speed == SPEED_1000)
5027 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5028 if (tp->link_config.active_duplex == DUPLEX_HALF)
5029 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5031 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5033 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5034 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5036 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5042 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5043 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5044 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5045 tw32_f(MAC_MI_MODE, tp->mi_mode);
5049 tw32_f(MAC_MODE, tp->mac_mode);
5052 tg3_phy_eee_adjust(tp, current_link_up);
5054 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5062 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5064 tp->link_config.active_speed == SPEED_1000 &&
5065 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5071 tg3_write_mem(tp,
5077 if (tg3_flag(tp, CLKREQ_BUG)) {
5078 if (tp->link_config.active_speed == SPEED_100 ||
5079 tp->link_config.active_speed == SPEED_10)
5080 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5083 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5087 tg3_test_and_report_link_chg(tp, current_link_up);
5156 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5236 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5237 tw32_f(MAC_MODE, tp->mac_mode);
5259 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5265 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5266 tw32_f(MAC_MODE, tp->mac_mode);
5280 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5281 tw32_f(MAC_MODE, tp->mac_mode);
5366 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5367 tw32_f(MAC_MODE, tp->mac_mode);
5408 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5418 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5422 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5431 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5438 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5439 tw32_f(MAC_MODE, tp->mac_mode);
5453 static void tg3_init_bcm8002(struct tg3 *tp)
5459 if (tg3_flag(tp, INIT_COMPLETE) &&
5464 tg3_writephy(tp, 0x16, 0x8007);
5467 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5475 tg3_writephy(tp, 0x10, 0x8411);
5478 tg3_writephy(tp, 0x11, 0x0a10);
5480 tg3_writephy(tp, 0x18, 0x00a0);
5481 tg3_writephy(tp, 0x16, 0x41ff);
5484 tg3_writephy(tp, 0x13, 0x0400);
5486 tg3_writephy(tp, 0x13, 0x0000);
5488 tg3_writephy(tp, 0x11, 0x0a50);
5490 tg3_writephy(tp, 0x11, 0x0a10);
5500 tg3_writephy(tp, 0x10, 0x8011);
5503 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5517 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5518 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5530 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5545 tg3_setup_flow_control(tp, 0, 0);
5554 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5561 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5562 tp->serdes_counter &&
5566 tp->serdes_counter--;
5577 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5578 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5598 tp->link_config.rmt_adv =
5601 tg3_setup_flow_control(tp, local_adv, remote_adv);
5603 tp->serdes_counter = 0;
5604 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5606 if (tp->serdes_counter)
5607 tp->serdes_counter--;
5629 tg3_setup_flow_control(tp, 0, 0);
5631 tp->phy_flags |=
5633 tp->serdes_counter =
5640 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5641 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5648 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5655 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5659 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5672 tp->link_config.rmt_adv =
5675 tg3_setup_flow_control(tp, local_adv, remote_adv);
5697 tg3_setup_flow_control(tp, 0, 0);
5702 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5705 tw32_f(MAC_MODE, tp->mac_mode);
5713 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5722 orig_pause_cfg = tp->link_config.active_flowctrl;
5723 orig_active_speed = tp->link_config.active_speed;
5724 orig_active_duplex = tp->link_config.active_duplex;
5726 if (!tg3_flag(tp, HW_AUTONEG) &&
5727 tp->link_up &&
5728 tg3_flag(tp, INIT_COMPLETE)) {
5744 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5745 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5746 tw32_f(MAC_MODE, tp->mac_mode);
5749 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5750 tg3_init_bcm8002(tp);
5757 tp->link_config.rmt_adv = 0;
5760 if (tg3_flag(tp, HW_AUTONEG))
5761 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5763 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5765 tp->napi[0].hw_status->status =
5767 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5782 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5783 tp->serdes_counter == 0) {
5784 tw32_f(MAC_MODE, (tp->mac_mode |
5787 tw32_f(MAC_MODE, tp->mac_mode);
5792 tp->link_config.active_speed = SPEED_1000;
5793 tp->link_config.active_duplex = DUPLEX_FULL;
5794 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5798 tp->link_config.active_speed = SPEED_UNKNOWN;
5799 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5800 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5805 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5806 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5808 orig_active_speed != tp->link_config.active_speed ||
5809 orig_active_duplex != tp->link_config.active_duplex)
5810 tg3_link_report(tp);
5816 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5825 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5826 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5827 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5831 tg3_phy_reset(tp);
5833 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5841 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5844 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5847 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5856 tw32_f(MAC_MODE, tp->mac_mode);
5859 tg3_clear_mac_status(tp);
5864 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5865 tw32_f(MAC_MODE, tp->mac_mode);
5868 tg3_clear_mac_status(tp);
5871 tg3_phy_reset(tp);
5873 tp->link_config.rmt_adv = 0;
5875 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5876 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5877 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5884 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5886 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5887 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5889 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5892 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5898 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5899 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5902 tg3_writephy(tp, MII_ADVERTISE, newadv);
5904 tg3_writephy(tp, MII_BMCR, bmcr);
5907 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5908 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5918 if (tp->link_config.duplex == DUPLEX_FULL)
5928 if (tp->link_up) {
5931 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5935 tg3_writephy(tp, MII_ADVERTISE, adv);
5936 tg3_writephy(tp, MII_BMCR, bmcr |
5940 tg3_carrier_off(tp);
5942 tg3_writephy(tp, MII_BMCR, new_bmcr);
5944 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5945 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5946 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5952 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5970 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5971 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5980 tp->link_config.rmt_adv =
5982 } else if (!tg3_flag(tp, 5780_CLASS)) {
5992 tg3_setup_flow_control(tp, local_adv, remote_adv);
5994 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5995 if (tp->link_config.active_duplex == DUPLEX_HALF)
5996 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5998 tw32_f(MAC_MODE, tp->mac_mode);
6003 tp->link_config.active_speed = current_speed;
6004 tp->link_config.active_duplex = current_duplex;
6006 tg3_test_and_report_link_chg(tp, current_link_up);
6010 static void tg3_serdes_parallel_detect(struct tg3 *tp)
6012 if (tp->serdes_counter) {
6014 tp->serdes_counter--;
6018 if (!tp->link_up &&
6019 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6022 tg3_readphy(tp, MII_BMCR, &bmcr);
6027 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6028 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6031 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6033 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6034 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6044 tg3_writephy(tp, MII_BMCR, bmcr);
6045 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6048 } else if (tp->link_up &&
6049 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6050 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6054 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6056 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6061 tg3_readphy(tp, MII_BMCR, &bmcr);
6062 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6064 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6070 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6075 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6076 err = tg3_setup_fiber_phy(tp, force_reset);
6077 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6078 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6080 err = tg3_setup_copper_phy(tp, force_reset);
6082 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6100 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6101 tg3_asic_rev(tp) == ASIC_REV_5762)
6106 if (tp->link_config.active_speed == SPEED_1000 &&
6107 tp->link_config.active_duplex == DUPLEX_HALF)
6114 if (!tg3_flag(tp, 5705_PLUS)) {
6115 if (tp->link_up) {
6117 tp->coal.stats_block_coalesce_usecs);
6123 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6125 if (!tp->link_up)
6127 tp->pwrmgmt_thresh;
6136 /* tp->lock must be held */
6137 static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts)
6149 /* tp->lock must be held */
6150 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6160 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6161 static inline void tg3_full_unlock(struct tg3 *tp);
6164 struct tg3 *tp = netdev_priv(dev);
6170 if (tg3_flag(tp, PTP_CAPABLE)) {
6176 if (tp->ptp_clock)
6177 info->phc_index = ptp_clock_index(tp->ptp_clock);
6192 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6212 tg3_full_lock(tp, 0);
6221 tg3_full_unlock(tp);
6228 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6230 tg3_full_lock(tp, 0);
6231 tp->ptp_adjust += delta;
6232 tg3_full_unlock(tp);
6241 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6243 tg3_full_lock(tp, 0);
6244 ns = tg3_refclk_read(tp, sts);
6245 ns += tp->ptp_adjust;
6246 tg3_full_unlock(tp);
6257 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6261 tg3_full_lock(tp, 0);
6262 tg3_refclk_write(tp, ns);
6263 tp->ptp_adjust = 0;
6264 tg3_full_unlock(tp);
6272 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6285 tg3_full_lock(tp, 0);
6296 netdev_warn(tp->dev,
6303 netdev_warn(tp->dev,
6322 tg3_full_unlock(tp);
6348 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6353 tp->ptp_adjust);
6356 /* tp->lock must be held */
6357 static void tg3_ptp_init(struct tg3 *tp)
6359 if (!tg3_flag(tp, PTP_CAPABLE))
6363 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6364 tp->ptp_adjust = 0;
6365 tp->ptp_info = tg3_ptp_caps;
6368 /* tp->lock must be held */
6369 static void tg3_ptp_resume(struct tg3 *tp)
6371 if (!tg3_flag(tp, PTP_CAPABLE))
6374 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6375 tp->ptp_adjust = 0;
6378 static void tg3_ptp_fini(struct tg3 *tp)
6380 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6383 ptp_clock_unregister(tp->ptp_clock);
6384 tp->ptp_clock = NULL;
6385 tp->ptp_adjust = 0;
6388 static inline int tg3_irq_sync(struct tg3 *tp)
6390 return tp->irq_sync;
6393 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6402 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6404 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6405 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6406 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6407 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6408 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6409 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6410 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6411 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6412 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6413 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6414 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6415 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6416 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6417 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6418 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6419 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6420 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6421 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6422 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6424 if (tg3_flag(tp, SUPPORT_MSIX))
6425 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6427 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6428 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6429 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6430 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6431 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6432 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6433 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6434 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6436 if (!tg3_flag(tp, 5705_PLUS)) {
6437 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6438 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6439 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6442 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6443 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6444 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6445 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6446 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6448 if (tg3_flag(tp, NVRAM))
6449 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6452 static void tg3_dump_state(struct tg3 *tp)
6460 if (tp->pdev->error_state != pci_channel_io_normal) {
6461 netdev_err(tp->dev, "PCI channel ERROR!\n");
6469 if (tg3_flag(tp, PCI_EXPRESS)) {
6474 tg3_dump_legacy_regs(tp, regs);
6481 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6488 for (i = 0; i < tp->irq_cnt; i++) {
6489 struct tg3_napi *tnapi = &tp->napi[i];
6492 netdev_err(tp->dev,
6503 netdev_err(tp->dev,
6522 static void tg3_tx_recover(struct tg3 *tp)
6524 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6525 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6527 netdev_warn(tp->dev,
6533 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6550 struct tg3 *tp = tnapi->tp;
6554 int index = tnapi - tp->napi;
6557 if (tg3_flag(tp, ENABLE_TSS))
6560 txq = netdev_get_tx_queue(tp->dev, index);
6568 tg3_tx_recover(tp);
6577 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6582 pci_unmap_single(tp->pdev,
6602 pci_unmap_page(tp->pdev,
6622 tg3_tx_recover(tp);
6656 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6658 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6664 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6682 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6694 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6697 data_size = tp->rx_pkt_map_sz;
6701 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6717 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6729 mapping = pci_map_single(tp->pdev,
6730 data + TG3_RX_OFFSET(tp),
6733 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6756 struct tg3 *tp = tnapi->tp;
6759 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6764 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6772 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6823 struct tg3 *tp = tnapi->tp;
6854 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6860 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6879 prefetch(data + TG3_RX_OFFSET(tp));
6891 if (len > TG3_RX_COPY_THRESH(tp)) {
6895 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6900 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6915 skb_reserve(skb, TG3_RX_OFFSET(tp));
6920 skb = netdev_alloc_skb(tp->dev,
6926 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6928 data + TG3_RX_OFFSET(tp),
6930 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6935 tg3_hwclock_to_timestamp(tp, tstamp,
6938 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6946 skb->protocol = eth_type_trans(skb, tp->dev);
6948 if (len > (tp->dev->mtu + ETH_HLEN) &&
6956 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6968 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6970 tp->rx_std_ring_mask;
6978 sw_idx &= tp->rx_ret_ring_mask;
6992 if (!tg3_flag(tp, ENABLE_RSS)) {
6998 tp->rx_std_ring_mask;
7004 tp->rx_jmb_ring_mask;
7014 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
7015 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
7017 if (tnapi != &tp->napi[1]) {
7018 tp->rx_refill = true;
7019 napi_schedule(&tp->napi[1].napi);
7026 static void tg3_poll_link(struct tg3 *tp)
7029 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7030 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7035 spin_lock(&tp->lock);
7036 if (tg3_flag(tp, USE_PHYLIB)) {
7044 tg3_setup_phy(tp, false);
7045 spin_unlock(&tp->lock);
7050 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7071 cpycnt = tp->rx_std_ring_mask + 1 -
7075 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7110 tp->rx_std_ring_mask;
7112 tp->rx_std_ring_mask;
7129 cpycnt = tp->rx_jmb_ring_mask + 1 -
7133 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7168 tp->rx_jmb_ring_mask;
7170 tp->rx_jmb_ring_mask;
7178 struct tg3 *tp = tnapi->tp;
7183 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7197 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7198 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7203 tp->rx_refill = false;
7204 for (i = 1; i <= tp->rxq_cnt; i++)
7205 err |= tg3_rx_prodring_xfer(tp, dpr,
7206 &tp->napi[i].prodring);
7219 tw32_f(HOSTCC_MODE, tp->coal_now);
7225 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7227 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7228 schedule_work(&tp->reset_task);
7231 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7233 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7234 cancel_work_sync(&tp->reset_task);
7235 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7241 struct tg3 *tp = tnapi->tp;
7248 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7254 /* tp->last_tag is used in tg3_int_reenable() below
7269 if (tnapi == &tp->napi[1] && tp->rx_refill)
7279 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7280 tw32(HOSTCC_MODE, tp->coalesce_mode |
7288 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
7294 tg3_reset_task_schedule(tp);
7298 static void tg3_process_error(struct tg3 *tp)
7303 if (tg3_flag(tp, ERROR_PROCESSED))
7309 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7314 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7319 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7326 tg3_dump_state(tp);
7328 tg3_flag_set(tp, ERROR_PROCESSED);
7329 tg3_reset_task_schedule(tp);
7335 struct tg3 *tp = tnapi->tp;
7341 tg3_process_error(tp);
7343 tg3_poll_link(tp);
7347 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7353 if (tg3_flag(tp, TAGGED_STATUS)) {
7354 /* tp->last_tag is used in tg3_int_reenable() below
7371 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
7377 tg3_reset_task_schedule(tp);
7381 static void tg3_napi_disable(struct tg3 *tp)
7385 for (i = tp->irq_cnt - 1; i >= 0; i--)
7386 napi_disable(&tp->napi[i].napi);
7389 static void tg3_napi_enable(struct tg3 *tp)
7393 for (i = 0; i < tp->irq_cnt; i++)
7394 napi_enable(&tp->napi[i].napi);
7397 static void tg3_napi_init(struct tg3 *tp)
7401 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7402 for (i = 1; i < tp->irq_cnt; i++)
7403 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7406 static void tg3_napi_fini(struct tg3 *tp)
7410 for (i = 0; i < tp->irq_cnt; i++)
7411 netif_napi_del(&tp->napi[i].napi);
7414 static inline void tg3_netif_stop(struct tg3 *tp)
7416 netif_trans_update(tp->dev); /* prevent tx timeout */
7417 tg3_napi_disable(tp);
7418 netif_carrier_off(tp->dev);
7419 netif_tx_disable(tp->dev);
7422 /* tp->lock must be held */
7423 static inline void tg3_netif_start(struct tg3 *tp)
7425 tg3_ptp_resume(tp);
7431 netif_tx_wake_all_queues(tp->dev);
7433 if (tp->link_up)
7434 netif_carrier_on(tp->dev);
7436 tg3_napi_enable(tp);
7437 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7438 tg3_enable_ints(tp);
7441 static void tg3_irq_quiesce(struct tg3 *tp)
7442 __releases(tp->lock)
7443 __acquires(tp->lock)
7447 BUG_ON(tp->irq_sync);
7449 tp->irq_sync = 1;
7452 spin_unlock_bh(&tp->lock);
7454 for (i = 0; i < tp->irq_cnt; i++)
7455 synchronize_irq(tp->napi[i].irq_vec);
7457 spin_lock_bh(&tp->lock);
7465 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7467 spin_lock_bh(&tp->lock);
7469 tg3_irq_quiesce(tp);
7472 static inline void tg3_full_unlock(struct tg3 *tp)
7474 spin_unlock_bh(&tp->lock);
7483 struct tg3 *tp = tnapi->tp;
7489 if (likely(!tg3_irq_sync(tp)))
7502 struct tg3 *tp = tnapi->tp;
7515 if (likely(!tg3_irq_sync(tp)))
7524 struct tg3 *tp = tnapi->tp;
7534 if (tg3_flag(tp, CHIP_RESETTING) ||
7553 if (tg3_irq_sync(tp))
7573 struct tg3 *tp = tnapi->tp;
7583 if (tg3_flag(tp, CHIP_RESETTING) ||
7611 if (tg3_irq_sync(tp))
7626 struct tg3 *tp = tnapi->tp;
7631 tg3_disable_ints(tp);
7641 struct tg3 *tp = netdev_priv(dev);
7643 if (tg3_irq_sync(tp))
7646 for (i = 0; i < tp->irq_cnt; i++)
7647 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7653 struct tg3 *tp = netdev_priv(dev);
7655 if (netif_msg_tx_err(tp)) {
7657 tg3_dump_state(tp);
7660 tg3_reset_task_schedule(tp);
7674 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7677 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7686 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7690 if (tg3_flag(tp, 40BIT_DMA_BUG))
7712 struct tg3 *tp = tnapi->tp;
7715 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7721 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7724 if (tg3_40bit_overflow_test(tp, map, len))
7727 if (tp->dma_limit) {
7730 while (len > tp->dma_limit && *budget) {
7731 u32 frag_len = tp->dma_limit;
7732 len -= tp->dma_limit;
7736 len += tp->dma_limit / 2;
7737 frag_len = tp->dma_limit / 2;
7780 pci_unmap_single(tnapi->tp->pdev,
7797 pci_unmap_page(tnapi->tp->pdev,
7815 struct tg3 *tp = tnapi->tp;
7820 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7834 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7837 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7877 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7899 segs = skb_gso_segment(skb, tp->dev->features &
7908 tg3_start_xmit(seg, tp->dev);
7920 struct tg3 *tp = netdev_priv(dev);
7934 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7935 if (tg3_flag(tp, ENABLE_TSS))
7941 * and TX reclaim runs via tp->napi.poll inside of a software
7977 return tg3_tso_bug(tp, tnapi, txq, skb);
7983 tg3_flag(tp, TSO_BUG)) {
7985 return tg3_tso_bug(tp, tnapi, txq, skb);
8000 if (tg3_flag(tp, HW_TSO_1) ||
8001 tg3_flag(tp, HW_TSO_2) ||
8002 tg3_flag(tp, HW_TSO_3)) {
8010 if (tg3_flag(tp, HW_TSO_3)) {
8015 } else if (tg3_flag(tp, HW_TSO_2))
8017 else if (tg3_flag(tp, HW_TSO_1) ||
8018 tg3_asic_rev(tp) == ASIC_REV_5705) {
8046 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8056 tg3_flag(tp, TX_TSTAMP_EN)) {
8063 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
8064 if (pci_dma_mapping_error(tp->pdev, mapping))
8073 if (tg3_flag(tp, 5701_DMA_BUG))
8083 if (!tg3_flag(tp, HW_TSO_1) &&
8084 !tg3_flag(tp, HW_TSO_2) &&
8085 !tg3_flag(tp, HW_TSO_3))
8096 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8102 if (dma_mapping_error(&tp->pdev->dev, mapping))
8128 return tg3_tso_bug(tp, tnapi, txq, skb);
8178 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8181 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8184 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8186 if (!tg3_flag(tp, 5705_PLUS))
8187 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8189 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8190 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8192 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8194 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8196 if (tg3_flag(tp, 5705_PLUS) ||
8197 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8198 tg3_asic_rev(tp) == ASIC_REV_5700)
8199 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8202 tw32(MAC_MODE, tp->mac_mode);
8206 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8210 tg3_phy_toggle_apd(tp, false);
8211 tg3_phy_toggle_automdix(tp, false);
8213 if (extlpbk && tg3_phy_set_extloopbk(tp))
8225 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8235 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8236 tg3_readphy(tp, MII_CTRL1000, &val);
8239 tg3_writephy(tp, MII_CTRL1000, val);
8243 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8248 tg3_writephy(tp, MII_BMCR, bmcr);
8251 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8252 tg3_readphy(tp, MII_BMCR, &bmcr);
8256 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8257 tg3_asic_rev(tp) == ASIC_REV_5785) {
8258 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8263 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8267 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8268 tg3_flag(tp, 5780_CLASS)) {
8271 tw32_f(MAC_RX_MODE, tp->rx_mode);
8274 mac_mode = tp->mac_mode &
8281 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8282 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8289 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8301 struct tg3 *tp = netdev_priv(dev);
8304 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8307 spin_lock_bh(&tp->lock);
8308 tg3_mac_loopback(tp, true);
8309 netif_carrier_on(tp->dev);
8310 spin_unlock_bh(&tp->lock);
8313 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8316 spin_lock_bh(&tp->lock);
8317 tg3_mac_loopback(tp, false);
8319 tg3_setup_phy(tp, true);
8320 spin_unlock_bh(&tp->lock);
8328 struct tg3 *tp = netdev_priv(dev);
8330 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8346 static void tg3_rx_prodring_free(struct tg3 *tp,
8351 if (tpr != &tp->napi[0].prodring) {
8353 i = (i + 1) & tp->rx_std_ring_mask)
8354 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8355 tp->rx_pkt_map_sz);
8357 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8360 i = (i + 1) & tp->rx_jmb_ring_mask) {
8361 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8369 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8370 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8371 tp->rx_pkt_map_sz);
8373 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8374 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8375 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8384 * end up in the driver. tp->{tx,}lock are held and thus
8387 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8397 if (tpr != &tp->napi[0].prodring) {
8399 TG3_RX_STD_BUFF_RING_SIZE(tp));
8402 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8407 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8410 if (tg3_flag(tp, 5780_CLASS) &&
8411 tp->dev->mtu > ETH_DATA_LEN)
8413 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8419 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8430 for (i = 0; i < tp->rx_pending; i++) {
8433 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8435 netdev_warn(tp->dev,
8438 "successfully\n", i, tp->rx_pending);
8441 tp->rx_pending = i;
8446 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8449 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8451 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8454 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8465 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8468 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8470 netdev_warn(tp->dev,
8473 "successfully\n", i, tp->rx_jumbo_pending);
8476 tp->rx_jumbo_pending = i;
8485 tg3_rx_prodring_free(tp, tpr);
8489 static void tg3_rx_prodring_fini(struct tg3 *tp,
8497 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8502 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8508 static int tg3_rx_prodring_init(struct tg3 *tp,
8511 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8516 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8517 TG3_RX_STD_RING_BYTES(tp),
8523 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8524 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8529 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8530 TG3_RX_JMB_RING_BYTES(tp),
8540 tg3_rx_prodring_fini(tp, tpr);
8548 * end up in the driver. tp->{tx,}lock is not held and we are not
8551 static void tg3_free_rings(struct tg3 *tp)
8555 for (j = 0; j < tp->irq_cnt; j++) {
8556 struct tg3_napi *tnapi = &tp->napi[j];
8558 tg3_rx_prodring_free(tp, &tnapi->prodring);
8574 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8582 * end up in the driver. tp->{tx,}lock are held and thus
8585 static int tg3_init_rings(struct tg3 *tp)
8590 tg3_free_rings(tp);
8592 for (i = 0; i < tp->irq_cnt; i++) {
8593 struct tg3_napi *tnapi = &tp->napi[i];
8608 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8611 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8612 tg3_free_rings(tp);
8620 static void tg3_mem_tx_release(struct tg3 *tp)
8624 for (i = 0; i < tp->irq_max; i++) {
8625 struct tg3_napi *tnapi = &tp->napi[i];
8628 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8638 static int tg3_mem_tx_acquire(struct tg3 *tp)
8641 struct tg3_napi *tnapi = &tp->napi[0];
8646 if (tg3_flag(tp, ENABLE_TSS))
8649 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8656 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8667 tg3_mem_tx_release(tp);
8671 static void tg3_mem_rx_release(struct tg3 *tp)
8675 for (i = 0; i < tp->irq_max; i++) {
8676 struct tg3_napi *tnapi = &tp->napi[i];
8678 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8683 dma_free_coherent(&tp->pdev->dev,
8684 TG3_RX_RCB_RING_BYTES(tp),
8691 static int tg3_mem_rx_acquire(struct tg3 *tp)
8695 limit = tp->rxq_cnt;
8700 if (tg3_flag(tp, ENABLE_RSS))
8704 struct tg3_napi *tnapi = &tp->napi[i];
8706 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8713 if (!i && tg3_flag(tp, ENABLE_RSS))
8716 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
8717 TG3_RX_RCB_RING_BYTES(tp),
8727 tg3_mem_rx_release(tp);
8735 static void tg3_free_consistent(struct tg3 *tp)
8739 for (i = 0; i < tp->irq_cnt; i++) {
8740 struct tg3_napi *tnapi = &tp->napi[i];
8743 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8750 tg3_mem_rx_release(tp);
8751 tg3_mem_tx_release(tp);
8753 /* tp->hw_stats can be referenced safely:
8755 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set.
8757 if (tp->hw_stats) {
8758 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8759 tp->hw_stats, tp->stats_mapping);
8760 tp->hw_stats = NULL;
8768 static int tg3_alloc_consistent(struct tg3 *tp)
8772 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
8774 &tp->stats_mapping, GFP_KERNEL);
8775 if (!tp->hw_stats)
8778 for (i = 0; i < tp->irq_cnt; i++) {
8779 struct tg3_napi *tnapi = &tp->napi[i];
8782 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
8791 if (tg3_flag(tp, ENABLE_RSS)) {
8820 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8826 tg3_free_consistent(tp);
8833 * clears. tp->lock is held.
8835 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8840 if (tg3_flag(tp, 5705_PLUS)) {
8862 if (pci_channel_offline(tp->pdev)) {
8863 dev_err(&tp->pdev->dev,
8877 dev_err(&tp->pdev->dev,
8886 /* tp->lock is held. */
8887 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8891 tg3_disable_ints(tp);
8893 if (pci_channel_offline(tp->pdev)) {
8894 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8895 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8900 tp->rx_mode &= ~RX_MODE_ENABLE;
8901 tw32_f(MAC_RX_MODE, tp->rx_mode);
8904 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8905 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8906 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8907 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8908 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8909 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8911 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8912 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8913 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8914 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8915 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8916 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8917 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8919 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8920 tw32_f(MAC_MODE, tp->mac_mode);
8923 tp->tx_mode &= ~TX_MODE_ENABLE;
8924 tw32_f(MAC_TX_MODE, tp->tx_mode);
8932 dev_err(&tp->pdev->dev,
8938 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8939 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8940 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8945 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8946 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8949 for (i = 0; i < tp->irq_cnt; i++) {
8950 struct tg3_napi *tnapi = &tp->napi[i];
8959 static void tg3_save_pci_state(struct tg3 *tp)
8961 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8965 static void tg3_restore_pci_state(struct tg3 *tp)
8970 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8971 tp->misc_host_ctrl);
8975 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8976 tg3_flag(tp, PCIX_MODE))
8979 if (tg3_flag(tp, ENABLE_APE))
8983 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8985 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8987 if (!tg3_flag(tp, PCI_EXPRESS)) {
8988 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8989 tp->pci_cacheline_sz);
8990 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8991 tp->pci_lat_timer);
8995 if (tg3_flag(tp, PCIX_MODE)) {
8998 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9001 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9005 if (tg3_flag(tp, 5780_CLASS)) {
9010 if (tg3_flag(tp, USING_MSI)) {
9013 pci_read_config_word(tp->pdev,
9014 tp->msi_cap + PCI_MSI_FLAGS,
9016 pci_write_config_word(tp->pdev,
9017 tp->msi_cap + PCI_MSI_FLAGS,
9025 static void tg3_override_clk(struct tg3 *tp)
9029 switch (tg3_asic_rev(tp)) {
9046 static void tg3_restore_clk(struct tg3 *tp)
9050 switch (tg3_asic_rev(tp)) {
9068 /* tp->lock is held. */
9069 static int tg3_chip_reset(struct tg3 *tp)
9070 __releases(tp->lock)
9071 __acquires(tp->lock)
9077 if (!pci_device_is_present(tp->pdev))
9080 tg3_nvram_lock(tp);
9082 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9087 tp->nvram_lock_cnt = 0;
9093 tg3_save_pci_state(tp);
9095 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9096 tg3_flag(tp, 5755_PLUS))
9105 write_op = tp->write32;
9107 tp->write32 = tg3_write32;
9115 tg3_flag_set(tp, CHIP_RESETTING);
9116 for (i = 0; i < tp->irq_cnt; i++) {
9117 struct tg3_napi *tnapi = &tp->napi[i];
9127 tg3_full_unlock(tp);
9129 for (i = 0; i < tp->irq_cnt; i++)
9130 synchronize_irq(tp->napi[i].irq_vec);
9132 tg3_full_lock(tp, 0);
9134 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9142 if (tg3_flag(tp, PCI_EXPRESS)) {
9144 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9145 !tg3_flag(tp, 57765_PLUS) &&
9150 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9156 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9167 tg3_override_clk(tp);
9170 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9176 tp->write32 = write_op;
9199 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9203 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9206 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9214 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9215 pci_write_config_dword(tp->pdev, 0xc4,
9225 if (!tg3_flag(tp, CPMU_PRESENT))
9227 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9230 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9237 tg3_restore_pci_state(tp);
9239 tg3_flag_clear(tp, CHIP_RESETTING);
9240 tg3_flag_clear(tp, ERROR_PROCESSED);
9243 if (tg3_flag(tp, 5780_CLASS))
9247 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9248 tg3_stop_fw(tp);
9252 if (tg3_flag(tp, IS_SSB_CORE)) {
9258 tg3_stop_fw(tp);
9259 tg3_halt_cpu(tp, RX_CPU_BASE);
9262 err = tg3_poll_fw(tp);
9266 tw32(GRC_MODE, tp->grc_mode);
9268 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9274 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9275 tg3_asic_rev(tp) == ASIC_REV_5705) {
9276 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9277 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9278 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9279 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9282 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9283 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9284 val = tp->mac_mode;
9285 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9286 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9287 val = tp->mac_mode;
9294 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9296 tg3_mdio_start(tp);
9298 if (tg3_flag(tp, PCI_EXPRESS) &&
9299 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9300 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9301 !tg3_flag(tp, 57765_PLUS)) {
9307 tg3_restore_clk(tp);
9312 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
9319 tg3_flag_clear(tp, ENABLE_ASF);
9320 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9323 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9324 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9328 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9330 tg3_flag_set(tp, ENABLE_ASF);
9331 tp->last_event_jiffies = jiffies;
9332 if (tg3_flag(tp, 5750_PLUS))
9333 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9335 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9337 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9339 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9350 /* tp->lock is held. */
9351 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9355 tg3_stop_fw(tp);
9357 tg3_write_sig_pre_reset(tp, kind);
9359 tg3_abort_hw(tp, silent);
9360 err = tg3_chip_reset(tp);
9362 __tg3_set_mac_addr(tp, false);
9364 tg3_write_sig_legacy(tp, kind);
9365 tg3_write_sig_post_reset(tp, kind);
9367 if (tp->hw_stats) {
9369 tg3_get_nstats(tp, &tp->net_stats_prev);
9370 tg3_get_estats(tp, &tp->estats_prev);
9373 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9376 struct tg3_napi *tnapi = &tp->napi[i];
9388 struct tg3 *tp = netdev_priv(dev);
9401 if (tg3_flag(tp, ENABLE_ASF)) {
9414 spin_lock_bh(&tp->lock);
9415 __tg3_set_mac_addr(tp, skip_mac_1);
9417 spin_unlock_bh(&tp->lock);
9422 /* tp->lock is held. */
9423 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9427 tg3_write_mem(tp,
9430 tg3_write_mem(tp,
9433 tg3_write_mem(tp,
9437 if (!tg3_flag(tp, 5705_PLUS))
9438 tg3_write_mem(tp,
9444 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9448 if (!tg3_flag(tp, ENABLE_TSS)) {
9457 for (; i < tp->txq_cnt; i++) {
9469 for (; i < tp->irq_max - 1; i++) {
9476 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9479 u32 limit = tp->rxq_cnt;
9481 if (!tg3_flag(tp, ENABLE_RSS)) {
9503 for (; i < tp->irq_max - 1; i++) {
9510 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9512 tg3_coal_tx_init(tp, ec);
9513 tg3_coal_rx_init(tp, ec);
9515 if (!tg3_flag(tp, 5705_PLUS)) {
9521 if (!tp->link_up)
9528 /* tp->lock is held. */
9529 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9534 if (!tg3_flag(tp, 5705_PLUS))
9536 else if (tg3_flag(tp, 5717_PLUS))
9538 else if (tg3_flag(tp, 57765_CLASS) ||
9539 tg3_asic_rev(tp) == ASIC_REV_5762)
9546 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9550 /* tp->lock is held. */
9551 static void tg3_tx_rcbs_init(struct tg3 *tp)
9556 if (tg3_flag(tp, ENABLE_TSS))
9559 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9560 struct tg3_napi *tnapi = &tp->napi[i];
9565 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9571 /* tp->lock is held. */
9572 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9577 if (tg3_flag(tp, 5717_PLUS))
9579 else if (!tg3_flag(tp, 5705_PLUS))
9581 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9582 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9583 tg3_flag(tp, 57765_CLASS))
9590 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9594 /* tp->lock is held. */
9595 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9600 if (tg3_flag(tp, ENABLE_RSS))
9603 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9604 struct tg3_napi *tnapi = &tp->napi[i];
9609 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9610 (tp->rx_ret_ring_mask + 1) <<
9615 /* tp->lock is held. */
9616 static void tg3_rings_reset(struct tg3 *tp)
9620 struct tg3_napi *tnapi = &tp->napi[0];
9622 tg3_tx_rcbs_disable(tp);
9624 tg3_rx_ret_rcbs_disable(tp);
9627 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9628 tp->napi[0].chk_msi_cnt = 0;
9629 tp->napi[0].last_rx_cons = 0;
9630 tp->napi[0].last_tx_cons = 0;
9633 if (tg3_flag(tp, SUPPORT_MSIX)) {
9634 for (i = 1; i < tp->irq_max; i++) {
9635 tp->napi[i].tx_prod = 0;
9636 tp->napi[i].tx_cons = 0;
9637 if (tg3_flag(tp, ENABLE_TSS))
9638 tw32_mailbox(tp->napi[i].prodmbox, 0);
9639 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9640 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9641 tp->napi[i].chk_msi_cnt = 0;
9642 tp->napi[i].last_rx_cons = 0;
9643 tp->napi[i].last_tx_cons = 0;
9645 if (!tg3_flag(tp, ENABLE_TSS))
9646 tw32_mailbox(tp->napi[0].prodmbox, 0);
9648 tp->napi[0].tx_prod = 0;
9649 tp->napi[0].tx_cons = 0;
9650 tw32_mailbox(tp->napi[0].prodmbox, 0);
9651 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9655 if (!tg3_flag(tp, 5705_PLUS)) {
9672 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9682 tg3_tx_rcbs_init(tp);
9683 tg3_rx_ret_rcbs_init(tp);
9686 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9690 if (!tg3_flag(tp, 5750_PLUS) ||
9691 tg3_flag(tp, 5780_CLASS) ||
9692 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9693 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9694 tg3_flag(tp, 57765_PLUS))
9696 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9697 tg3_asic_rev(tp) == ASIC_REV_5787)
9702 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9703 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9708 if (tg3_flag(tp, 57765_PLUS))
9711 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9716 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9721 if (tg3_flag(tp, 57765_PLUS))
9749 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9760 struct tg3 *tp = netdev_priv(dev);
9763 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9770 if (!tg3_flag(tp, ENABLE_ASF))
9779 tg3_set_multi(tp, 1);
9782 tg3_set_multi(tp, 0);
9805 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9813 __tg3_set_one_mac_addr(tp, ha->addr,
9814 i + TG3_UCAST_ADDR_IDX(tp));
9819 if (rx_mode != tp->rx_mode) {
9820 tp->rx_mode = rx_mode;
9826 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9831 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9834 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9838 if (!tg3_flag(tp, SUPPORT_MSIX))
9841 if (tp->rxq_cnt == 1) {
9842 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9848 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9853 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9856 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9862 u32 val = tp->rss_ind_tbl[i];
9866 val |= tp->rss_ind_tbl[i];
9873 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9875 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9881 /* tp->lock is held. */
9882 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9886 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9888 tg3_disable_ints(tp);
9890 tg3_stop_fw(tp);
9892 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9894 if (tg3_flag(tp, INIT_COMPLETE))
9895 tg3_abort_hw(tp, 1);
9897 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9898 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9899 tg3_phy_pull_config(tp);
9900 tg3_eee_pull_config(tp, NULL);
9901 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9905 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9906 tg3_setup_eee(tp);
9909 tg3_phy_reset(tp);
9911 err = tg3_chip_reset(tp);
9915 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9917 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9938 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9953 if (tg3_flag(tp, L1PLLPD_EN)) {
9967 if (tg3_flag(tp, 57765_CLASS)) {
9968 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9983 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
10017 if (!tg3_flag(tp, CPMU_PRESENT)) {
10018 if (!tg3_flag(tp, PCI_EXPRESS))
10019 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
10020 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
10023 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
10024 tg3_flag(tp, PCIX_MODE)) {
10030 if (tg3_flag(tp, ENABLE_APE)) {
10041 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
10053 err = tg3_init_rings(tp);
10057 if (tg3_flag(tp, 57765_PLUS)) {
10060 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
10062 if (!tg3_flag(tp, 57765_CLASS) &&
10063 tg3_asic_rev(tp) != ASIC_REV_5717 &&
10064 tg3_asic_rev(tp) != ASIC_REV_5762)
10066 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10067 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
10068 tg3_asic_rev(tp) != ASIC_REV_5761) {
10072 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10075 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10079 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
10087 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
10090 if (tp->rxptpctl)
10092 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10094 if (tg3_flag(tp, PTP_CAPABLE))
10097 tw32(GRC_MODE, tp->grc_mode | val);
10103 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10104 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {
10116 if (tg3_flag(tp, 5750_PLUS)) {
10118 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10120 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10126 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10129 fw_len = tp->fw_len;
10137 if (tp->dev->mtu <= ETH_DATA_LEN) {
10139 tp->bufmgr_config.mbuf_read_dma_low_water);
10141 tp->bufmgr_config.mbuf_mac_rx_low_water);
10143 tp->bufmgr_config.mbuf_high_water);
10146 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10148 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10150 tp->bufmgr_config.mbuf_high_water_jumbo);
10153 tp->bufmgr_config.dma_low_water);
10155 tp->bufmgr_config.dma_high_water);
10158 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10160 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10161 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10162 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10163 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10172 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10176 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10179 tg3_setup_rxbd_thresholds(tp);
10202 if (!tg3_flag(tp, 5717_PLUS))
10207 if (!tg3_flag(tp, 5705_PLUS))
10214 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10215 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10217 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10222 val = TG3_RX_JMB_RING_SIZE(tp) <<
10226 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10227 tg3_flag(tp, 57765_CLASS) ||
10228 tg3_asic_rev(tp) == ASIC_REV_5762)
10236 if (tg3_flag(tp, 57765_PLUS)) {
10237 val = TG3_RX_STD_RING_SIZE(tp);
10247 tpr->rx_std_prod_idx = tp->rx_pending;
10251 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10254 tg3_rings_reset(tp);
10257 __tg3_set_mac_addr(tp, false);
10261 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10270 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10271 tg3_asic_rev(tp) == ASIC_REV_5762)
10291 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10294 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10295 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10296 tg3_asic_rev(tp) == ASIC_REV_57780)
10301 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10302 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10303 if (tg3_flag(tp, TSO_CAPABLE) &&
10304 tg3_asic_rev(tp) == ASIC_REV_5705) {
10307 !tg3_flag(tp, IS_5788)) {
10312 if (tg3_flag(tp, PCI_EXPRESS))
10315 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10316 tp->dma_limit = 0;
10317 if (tp->dev->mtu <= ETH_DATA_LEN) {
10319 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10323 if (tg3_flag(tp, HW_TSO_1) ||
10324 tg3_flag(tp, HW_TSO_2) ||
10325 tg3_flag(tp, HW_TSO_3))
10328 if (tg3_flag(tp, 57765_PLUS) ||
10329 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10330 tg3_asic_rev(tp) == ASIC_REV_57780)
10333 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10334 tg3_asic_rev(tp) == ASIC_REV_5762)
10337 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10338 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10339 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10340 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10341 tg3_flag(tp, 57765_PLUS)) {
10344 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10350 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10351 tg3_asic_rev(tp) == ASIC_REV_5762) {
10362 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10363 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10364 tg3_asic_rev(tp) == ASIC_REV_5762) {
10367 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10379 if (tg3_flag(tp, 5750_PLUS)) {
10384 tg3_flag(tp, TSO_CAPABLE)) {
10405 __tg3_set_coalesce(tp, &tp->coal);
10407 if (!tg3_flag(tp, 5705_PLUS)) {
10413 ((u64) tp->stats_mapping >> 32));
10415 ((u64) tp->stats_mapping & 0xffffffff));
10424 tg3_write_mem(tp, i, 0);
10429 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10433 if (!tg3_flag(tp, 5705_PLUS))
10436 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10437 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10443 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10446 if (tg3_flag(tp, ENABLE_APE))
10447 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10448 if (!tg3_flag(tp, 5705_PLUS) &&
10449 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10450 tg3_asic_rev(tp) != ASIC_REV_5700)
10451 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10452 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10455 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10461 if (!tg3_flag(tp, IS_NIC)) {
10468 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10472 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10475 tp->grc_local_ctrl &= ~gpio_mask;
10476 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10479 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10480 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10483 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10486 if (tg3_flag(tp, USING_MSIX)) {
10489 if (tp->irq_cnt > 1)
10491 if (!tg3_flag(tp, 1SHOT_MSI))
10496 if (!tg3_flag(tp, 5705_PLUS)) {
10507 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10508 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10509 if (tg3_flag(tp, TSO_CAPABLE) &&
10510 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10511 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10514 !tg3_flag(tp, IS_5788)) {
10520 if (tg3_flag(tp, 5755_PLUS))
10523 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10529 if (tg3_flag(tp, PCIX_MODE)) {
10532 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10534 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10537 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10541 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10548 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10549 tg3_asic_rev(tp) == ASIC_REV_5720) {
10551 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10556 val |= tg3_lso_rd_dma_workaround_bit(tp);
10558 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10563 if (!tg3_flag(tp, 5705_PLUS))
10566 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10575 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10579 if (tg3_flag(tp, HW_TSO_1) ||
10580 tg3_flag(tp, HW_TSO_2) ||
10581 tg3_flag(tp, HW_TSO_3))
10584 if (tg3_flag(tp, ENABLE_TSS))
10589 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10590 err = tg3_load_5701_a0_firmware_fix(tp);
10595 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10599 tg3_load_57766_firmware(tp);
10602 if (tg3_flag(tp, TSO_CAPABLE)) {
10603 err = tg3_load_tso_firmware(tp);
10608 tp->tx_mode = TX_MODE_ENABLE;
10610 if (tg3_flag(tp, 5755_PLUS) ||
10611 tg3_asic_rev(tp) == ASIC_REV_5906)
10612 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10614 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10615 tg3_asic_rev(tp) == ASIC_REV_5762) {
10617 tp->tx_mode &= ~val;
10618 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10621 tw32_f(MAC_TX_MODE, tp->tx_mode);
10624 if (tg3_flag(tp, ENABLE_RSS)) {
10627 tg3_rss_write_indir_tbl(tp);
10635 tp->rx_mode = RX_MODE_ENABLE;
10636 if (tg3_flag(tp, 5755_PLUS))
10637 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10639 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10640 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10642 if (tg3_flag(tp, ENABLE_RSS))
10643 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10650 tw32_f(MAC_RX_MODE, tp->rx_mode);
10653 tw32(MAC_LED_CTRL, tp->led_ctrl);
10656 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10660 tw32_f(MAC_RX_MODE, tp->rx_mode);
10663 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10664 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10665 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10673 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10680 if (tg3_flag(tp, 57765_CLASS))
10686 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10687 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10689 tg3_flag_set(tp, HW_AUTONEG);
10692 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10693 tg3_asic_rev(tp) == ASIC_REV_5714) {
10698 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10699 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10700 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10703 if (!tg3_flag(tp, USE_PHYLIB)) {
10704 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10705 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10707 err = tg3_setup_phy(tp, false);
10711 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10712 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10716 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10717 tg3_writephy(tp, MII_TG3_TEST1,
10719 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10724 __tg3_set_rx_mode(tp->dev);
10732 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10736 if (tg3_flag(tp, ENABLE_ASF))
10786 if (tg3_flag(tp, ENABLE_APE))
10788 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10791 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10797 * packet processing. Invoked with tp->lock held.
10799 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10805 tg3_enable_register_access(tp);
10806 tg3_poll_fw(tp);
10808 tg3_switch_clocks(tp);
10812 return tg3_reset_hw(tp, reset_phy);
10816 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10822 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10835 struct tg3 *tp = dev_get_drvdata(dev);
10838 spin_lock_bh(&tp->lock);
10839 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10841 spin_unlock_bh(&tp->lock);
10861 static void tg3_hwmon_close(struct tg3 *tp)
10863 if (tp->hwmon_dev) {
10864 hwmon_device_unregister(tp->hwmon_dev);
10865 tp->hwmon_dev = NULL;
10869 static void tg3_hwmon_open(struct tg3 *tp)
10873 struct pci_dev *pdev = tp->pdev;
10876 tg3_sd_scan_scratchpad(tp, ocirs);
10889 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10890 tp, tg3_groups);
10891 if (IS_ERR(tp->hwmon_dev)) {
10892 tp->hwmon_dev = NULL;
10897 static inline void tg3_hwmon_close(struct tg3 *tp) { }
10898 static inline void tg3_hwmon_open(struct tg3 *tp) { }
10909 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10911 struct tg3_hw_stats *sp = tp->hw_stats;
10913 if (!tp->link_up)
10929 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10935 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10937 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10956 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10957 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10958 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10959 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10975 static void tg3_chk_missed_msi(struct tg3 *tp)
10979 for (i = 0; i < tp->irq_cnt; i++) {
10980 struct tg3_napi *tnapi = &tp->napi[i];
11000 struct tg3 *tp = from_timer(tp, t, timer);
11002 spin_lock(&tp->lock);
11004 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {
11005 spin_unlock(&tp->lock);
11009 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
11010 tg3_flag(tp, 57765_CLASS))
11011 tg3_chk_missed_msi(tp);
11013 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
11018 if (!tg3_flag(tp, TAGGED_STATUS)) {
11023 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
11025 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
11027 tw32(HOSTCC_MODE, tp->coalesce_mode |
11032 spin_unlock(&tp->lock);
11033 tg3_reset_task_schedule(tp);
11039 if (!--tp->timer_counter) {
11040 if (tg3_flag(tp, 5705_PLUS))
11041 tg3_periodic_fetch_stats(tp);
11043 if (tp->setlpicnt && !--tp->setlpicnt)
11044 tg3_phy_eee_enable(tp);
11046 if (tg3_flag(tp, USE_LINKCHG_REG)) {
11053 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
11060 tg3_setup_phy(tp, false);
11061 } else if (tg3_flag(tp, POLL_SERDES)) {
11065 if (tp->link_up &&
11069 if (!tp->link_up &&
11075 if (!tp->serdes_counter) {
11077 (tp->mac_mode &
11080 tw32_f(MAC_MODE, tp->mac_mode);
11083 tg3_setup_phy(tp, false);
11085 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
11086 tg3_flag(tp, 5780_CLASS)) {
11087 tg3_serdes_parallel_detect(tp);
11088 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
11093 if (link_up != tp->link_up)
11094 tg3_setup_phy(tp, false);
11097 tp->timer_counter = tp->timer_multiplier;
11117 if (!--tp->asf_counter) {
11118 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
11119 tg3_wait_for_event_ack(tp);
11121 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
11123 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
11124 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11127 tg3_generate_fw_event(tp);
11129 tp->asf_counter = tp->asf_multiplier;
11133 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL);
11135 spin_unlock(&tp->lock);
11138 tp->timer.expires = jiffies + tp->timer_offset;
11139 add_timer(&tp->timer);
11142 static void tg3_timer_init(struct tg3 *tp)
11144 if (tg3_flag(tp, TAGGED_STATUS) &&
11145 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11146 !tg3_flag(tp, 57765_CLASS))
11147 tp->timer_offset = HZ;
11149 tp->timer_offset = HZ / 10;
11151 BUG_ON(tp->timer_offset > HZ);
11153 tp->timer_multiplier = (HZ / tp->timer_offset);
11154 tp->asf_multiplier = (HZ / tp->timer_offset) *
11157 timer_setup(&tp->timer, tg3_timer, 0);
11160 static void tg3_timer_start(struct tg3 *tp)
11162 tp->asf_counter = tp->asf_multiplier;
11163 tp->timer_counter = tp->timer_multiplier;
11165 tp->timer.expires = jiffies + tp->timer_offset;
11166 add_timer(&tp->timer);
11169 static void tg3_timer_stop(struct tg3 *tp)
11171 del_timer_sync(&tp->timer);
11175 * Invoked with tp->lock held.
11177 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11178 __releases(tp->lock)
11179 __acquires(tp->lock)
11183 err = tg3_init_hw(tp, reset_phy);
11185 netdev_err(tp->dev,
11187 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11188 tg3_full_unlock(tp);
11189 tg3_timer_stop(tp);
11190 tp->irq_sync = 0;
11191 tg3_napi_enable(tp);
11192 dev_close(tp->dev);
11193 tg3_full_lock(tp, 0);
11200 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11204 tg3_full_lock(tp, 0);
11206 if (tp->pcierr_recovery || !netif_running(tp->dev) ||
11207 tp->pdev->error_state != pci_channel_io_normal) {
11208 tg3_flag_clear(tp, RESET_TASK_PENDING);
11209 tg3_full_unlock(tp);
11214 tg3_full_unlock(tp);
11216 tg3_phy_stop(tp);
11218 tg3_netif_stop(tp);
11220 tg3_full_lock(tp, 1);
11222 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11223 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11224 tp->write32_rx_mbox = tg3_write_flush_reg32;
11225 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11226 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11229 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11230 err = tg3_init_hw(tp, true);
11232 tg3_full_unlock(tp);
11233 tp->irq_sync = 0;
11234 tg3_napi_enable(tp);
11238 tg3_flag_clear(tp, RESET_TASK_PENDING);
11239 dev_close(tp->dev);
11243 tg3_netif_start(tp);
11245 tg3_full_unlock(tp);
11248 tg3_phy_start(tp);
11250 tg3_flag_clear(tp, RESET_TASK_PENDING);
11255 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11260 struct tg3_napi *tnapi = &tp->napi[irq_num];
11262 if (tp->irq_cnt == 1)
11263 name = tp->dev->name;
11268 "%s-txrx-%d", tp->dev->name, irq_num);
11271 "%s-tx-%d", tp->dev->name, irq_num);
11274 "%s-rx-%d", tp->dev->name, irq_num);
11277 "%s-%d", tp->dev->name, irq_num);
11281 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11283 if (tg3_flag(tp, 1SHOT_MSI))
11288 if (tg3_flag(tp, TAGGED_STATUS))
11296 static int tg3_test_interrupt(struct tg3 *tp)
11298 struct tg3_napi *tnapi = &tp->napi[0];
11299 struct net_device *dev = tp->dev;
11306 tg3_disable_ints(tp);
11314 if (tg3_flag(tp, 57765_PLUS)) {
11325 tg3_enable_ints(tp);
11327 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11342 if (tg3_flag(tp, 57765_PLUS) &&
11349 tg3_disable_ints(tp);
11353 err = tg3_request_irq(tp, 0);
11360 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11373 static int tg3_test_msi(struct tg3 *tp)
11378 if (!tg3_flag(tp, USING_MSI))
11384 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11385 pci_write_config_word(tp->pdev, PCI_COMMAND,
11388 err = tg3_test_interrupt(tp);
11390 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11400 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11404 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11406 pci_disable_msi(tp->pdev);
11408 tg3_flag_clear(tp, USING_MSI);
11409 tp->napi[0].irq_vec = tp->pdev->irq;
11411 err = tg3_request_irq(tp, 0);
11418 tg3_full_lock(tp, 1);
11420 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11421 err = tg3_init_hw(tp, true);
11423 tg3_full_unlock(tp);
11426 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11431 static int tg3_request_firmware(struct tg3 *tp)
11435 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11436 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11437 tp->fw_needed);
11441 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11448 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11449 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11450 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11451 tp->fw_len, tp->fw_needed);
11452 release_firmware(tp->fw);
11453 tp->fw = NULL;
11458 tp->fw_needed = NULL;
11462 static u32 tg3_irq_count(struct tg3 *tp)
11464 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11472 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11478 static bool tg3_enable_msix(struct tg3 *tp)
11483 tp->txq_cnt = tp->txq_req;
11484 tp->rxq_cnt = tp->rxq_req;
11485 if (!tp->rxq_cnt)
11486 tp->rxq_cnt = netif_get_num_default_rss_queues();
11487 if (tp->rxq_cnt > tp->rxq_max)
11488 tp->rxq_cnt = tp->rxq_max;
11494 if (!tp->txq_req)
11495 tp->txq_cnt = 1;
11497 tp->irq_cnt = tg3_irq_count(tp);
11499 for (i = 0; i < tp->irq_max; i++) {
11504 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11507 } else if (rc < tp->irq_cnt) {
11508 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11509 tp->irq_cnt, rc);
11510 tp->irq_cnt = rc;
11511 tp->rxq_cnt = max(rc - 1, 1);
11512 if (tp->txq_cnt)
11513 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11516 for (i = 0; i < tp->irq_max; i++)
11517 tp->napi[i].irq_vec = msix_ent[i].vector;
11519 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11520 pci_disable_msix(tp->pdev);
11524 if (tp->irq_cnt == 1)
11527 tg3_flag_set(tp, ENABLE_RSS);
11529 if (tp->txq_cnt > 1)
11530 tg3_flag_set(tp, ENABLE_TSS);
11532 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11537 static void tg3_ints_init(struct tg3 *tp)
11539 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11540 !tg3_flag(tp, TAGGED_STATUS)) {
11544 netdev_warn(tp->dev,
11549 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11550 tg3_flag_set(tp, USING_MSIX);
11551 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11552 tg3_flag_set(tp, USING_MSI);
11554 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11556 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11558 if (!tg3_flag(tp, 1SHOT_MSI))
11563 if (!tg3_flag(tp, USING_MSIX)) {
11564 tp->irq_cnt = 1;
11565 tp->napi[0].irq_vec = tp->pdev->irq;
11568 if (tp->irq_cnt == 1) {
11569 tp->txq_cnt = 1;
11570 tp->rxq_cnt = 1;
11571 netif_set_real_num_tx_queues(tp->dev, 1);
11572 netif_set_real_num_rx_queues(tp->dev, 1);
11576 static void tg3_ints_fini(struct tg3 *tp)
11578 if (tg3_flag(tp, USING_MSIX))
11579 pci_disable_msix(tp->pdev);
11580 else if (tg3_flag(tp, USING_MSI))
11581 pci_disable_msi(tp->pdev);
11582 tg3_flag_clear(tp, USING_MSI);
11583 tg3_flag_clear(tp, USING_MSIX);
11584 tg3_flag_clear(tp, ENABLE_RSS);
11585 tg3_flag_clear(tp, ENABLE_TSS);
11588 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11591 struct net_device *dev = tp->dev;
11598 tg3_ints_init(tp);
11600 tg3_rss_check_indir_tbl(tp);
11605 err = tg3_alloc_consistent(tp);
11609 tg3_napi_init(tp);
11611 tg3_napi_enable(tp);
11613 for (i = 0; i < tp->irq_cnt; i++) {
11614 err = tg3_request_irq(tp, i);
11617 struct tg3_napi *tnapi = &tp->napi[i];
11625 tg3_full_lock(tp, 0);
11628 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11630 err = tg3_init_hw(tp, reset_phy);
11632 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11633 tg3_free_rings(tp);
11636 tg3_full_unlock(tp);
11641 if (test_irq && tg3_flag(tp, USING_MSI)) {
11642 err = tg3_test_msi(tp);
11645 tg3_full_lock(tp, 0);
11646 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11647 tg3_free_rings(tp);
11648 tg3_full_unlock(tp);
11653 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11661 tg3_phy_start(tp);
11663 tg3_hwmon_open(tp);
11665 tg3_full_lock(tp, 0);
11667 tg3_timer_start(tp);
11668 tg3_flag_set(tp, INIT_COMPLETE);
11669 tg3_enable_ints(tp);
11671 tg3_ptp_resume(tp);
11673 tg3_full_unlock(tp);
11687 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11688 struct tg3_napi *tnapi = &tp->napi[i];
11693 tg3_napi_disable(tp);
11694 tg3_napi_fini(tp);
11695 tg3_free_consistent(tp);
11698 tg3_ints_fini(tp);
11703 static void tg3_stop(struct tg3 *tp)
11707 tg3_reset_task_cancel(tp);
11708 tg3_netif_stop(tp);
11710 tg3_timer_stop(tp);
11712 tg3_hwmon_close(tp);
11714 tg3_phy_stop(tp);
11716 tg3_full_lock(tp, 1);
11718 tg3_disable_ints(tp);
11720 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11721 tg3_free_rings(tp);
11722 tg3_flag_clear(tp, INIT_COMPLETE);
11724 tg3_full_unlock(tp);
11726 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11727 struct tg3_napi *tnapi = &tp->napi[i];
11731 tg3_ints_fini(tp);
11733 tg3_napi_fini(tp);
11735 tg3_free_consistent(tp);
11740 struct tg3 *tp = netdev_priv(dev);
11743 if (tp->pcierr_recovery) {
11749 if (tp->fw_needed) {
11750 err = tg3_request_firmware(tp);
11751 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11753 netdev_warn(tp->dev, "EEE capability disabled\n");
11754 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11755 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11756 netdev_warn(tp->dev, "EEE capability restored\n");
11757 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11759 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11763 netdev_warn(tp->dev, "TSO capability disabled\n");
11764 tg3_flag_clear(tp, TSO_CAPABLE);
11765 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11766 netdev_notice(tp->dev, "TSO capability restored\n");
11767 tg3_flag_set(tp, TSO_CAPABLE);
11771 tg3_carrier_off(tp);
11773 err = tg3_power_up(tp);
11777 tg3_full_lock(tp, 0);
11779 tg3_disable_ints(tp);
11780 tg3_flag_clear(tp, INIT_COMPLETE);
11782 tg3_full_unlock(tp);
11784 err = tg3_start(tp,
11785 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11788 tg3_frob_aux_power(tp, false);
11789 pci_set_power_state(tp->pdev, PCI_D3hot);
11797 struct tg3 *tp = netdev_priv(dev);
11799 if (tp->pcierr_recovery) {
11805 tg3_stop(tp);
11807 if (pci_device_is_present(tp->pdev)) {
11808 tg3_power_down_prepare(tp);
11810 tg3_carrier_off(tp);
11820 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11822 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11824 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11825 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11826 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11829 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11830 tg3_writephy(tp, MII_TG3_TEST1,
11832 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11836 tp->phy_crc_errors += val;
11838 return tp->phy_crc_errors;
11848 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11850 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11851 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11932 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11934 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11935 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11980 tg3_calc_crc_errors(tp);
11996 for (i = 0; i < tp->irq_cnt; i++) {
11997 struct tg3_napi *tnapi = &tp->napi[i];
12015 struct tg3 *tp = netdev_priv(dev);
12021 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
12024 tg3_full_lock(tp, 0);
12026 tg3_dump_legacy_regs(tp, (u32 *)_p);
12028 tg3_full_unlock(tp);
12033 struct tg3 *tp = netdev_priv(dev);
12035 return tp->nvram_size;
12040 struct tg3 *tp = netdev_priv(dev);
12046 if (tg3_flag(tp, NO_NVRAM))
12056 if (tg3_flag(tp, CPMU_PRESENT)) {
12066 tg3_override_clk(tp);
12076 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
12088 ret = tg3_nvram_read_be32(tp, offset + i, &val);
12112 ret = tg3_nvram_read_be32(tp, b_offset, &val);
12122 tg3_restore_clk(tp);
12131 struct tg3 *tp = netdev_priv(dev);
12137 if (tg3_flag(tp, NO_NVRAM) ||
12146 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12160 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12177 ret = tg3_nvram_write_block(tp, offset, len, buf);
12188 struct tg3 *tp = netdev_priv(dev);
12191 if (tg3_flag(tp, USE_PHYLIB)) {
12193 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12195 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12203 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12207 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12221 advertising = tp->link_config.advertising;
12222 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12223 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12224 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12230 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12237 if (netif_running(dev) && tp->link_up) {
12238 cmd->base.speed = tp->link_config.active_speed;
12239 cmd->base.duplex = tp->link_config.active_duplex;
12242 tp->link_config.rmt_adv);
12244 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12245 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12255 cmd->base.phy_address = tp->phy_addr;
12256 cmd->base.autoneg = tp->link_config.autoneg;
12263 struct tg3 *tp = netdev_priv(dev);
12267 if (tg3_flag(tp, USE_PHYLIB)) {
12269 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12271 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12292 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12296 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12317 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12330 tg3_full_lock(tp, 0);
12332 tp->link_config.autoneg = cmd->base.autoneg;
12334 tp->link_config.advertising = (advertising |
12336 tp->link_config.speed = SPEED_UNKNOWN;
12337 tp->link_config.duplex = DUPLEX_UNKNOWN;
12339 tp->link_config.advertising = 0;
12340 tp->link_config.speed = speed;
12341 tp->link_config.duplex = cmd->base.duplex;
12344 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12346 tg3_warn_mgmt_link_flap(tp);
12349 tg3_setup_phy(tp, true);
12351 tg3_full_unlock(tp);
12358 struct tg3 *tp = netdev_priv(dev);
12361 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12362 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12367 struct tg3 *tp = netdev_priv(dev);
12369 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12374 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12381 struct tg3 *tp = netdev_priv(dev);
12382 struct device *dp = &tp->pdev->dev;
12387 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12393 tg3_flag_set(tp, WOL_ENABLE);
12395 tg3_flag_clear(tp, WOL_ENABLE);
12402 struct tg3 *tp = netdev_priv(dev);
12403 return tp->msg_enable;
12408 struct tg3 *tp = netdev_priv(dev);
12409 tp->msg_enable = value;
12414 struct tg3 *tp = netdev_priv(dev);
12420 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12423 tg3_warn_mgmt_link_flap(tp);
12425 if (tg3_flag(tp, USE_PHYLIB)) {
12426 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12428 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
12432 spin_lock_bh(&tp->lock);
12434 tg3_readphy(tp, MII_BMCR, &bmcr);
12435 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12437 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12438 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12442 spin_unlock_bh(&tp->lock);
12450 struct tg3 *tp = netdev_priv(dev);
12452 ering->rx_max_pending = tp->rx_std_ring_mask;
12453 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12454 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12460 ering->rx_pending = tp->rx_pending;
12461 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12462 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12466 ering->tx_pending = tp->napi[0].tx_pending;
12471 struct tg3 *tp = netdev_priv(dev);
12475 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12476 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12479 (tg3_flag(tp, TSO_BUG) &&
12484 tg3_phy_stop(tp);
12485 tg3_netif_stop(tp);
12489 tg3_full_lock(tp, irq_sync);
12491 tp->rx_pending = ering->rx_pending;
12493 if (tg3_flag(tp, MAX_RXPEND_64) &&
12494 tp->rx_pending > 63)
12495 tp->rx_pending = 63;
12497 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12498 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12500 for (i = 0; i < tp->irq_max; i++)
12501 tp->napi[i].tx_pending = ering->tx_pending;
12504 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12506 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
12507 tg3_asic_rev(tp) == ASIC_REV_5719 ||
12508 tg3_asic_rev(tp) == ASIC_REV_5720)
12511 err = tg3_restart_hw(tp, reset_phy);
12513 tg3_netif_start(tp);
12516 tg3_full_unlock(tp);
12519 tg3_phy_start(tp);
12526 struct tg3 *tp = netdev_priv(dev);
12528 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12530 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12535 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12543 struct tg3 *tp = netdev_priv(dev);
12547 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12548 tg3_warn_mgmt_link_flap(tp);
12550 if (tg3_flag(tp, USE_PHYLIB)) {
12553 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12558 tp->link_config.flowctrl = 0;
12561 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12564 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12567 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12571 tg3_flag_set(tp, PAUSE_AUTONEG);
12573 tg3_flag_clear(tp, PAUSE_AUTONEG);
12575 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12588 tg3_setup_flow_control(tp, 0, 0);
12594 tg3_netif_stop(tp);
12598 tg3_full_lock(tp, irq_sync);
12601 tg3_flag_set(tp, PAUSE_AUTONEG);
12603 tg3_flag_clear(tp, PAUSE_AUTONEG);
12605 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12607 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12609 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12611 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12614 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12616 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
12617 tg3_asic_rev(tp) == ASIC_REV_5719 ||
12618 tg3_asic_rev(tp) == ASIC_REV_5720)
12621 err = tg3_restart_hw(tp, reset_phy);
12623 tg3_netif_start(tp);
12626 tg3_full_unlock(tp);
12629 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12649 struct tg3 *tp = netdev_priv(dev);
12651 if (!tg3_flag(tp, SUPPORT_MSIX))
12656 if (netif_running(tp->dev))
12657 info->data = tp->rxq_cnt;
12674 struct tg3 *tp = netdev_priv(dev);
12676 if (tg3_flag(tp, SUPPORT_MSIX))
12684 struct tg3 *tp = netdev_priv(dev);
12693 indir[i] = tp->rss_ind_tbl[i];
12701 struct tg3 *tp = netdev_priv(dev);
12715 tp->rss_ind_tbl[i] = indir[i];
12717 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12723 tg3_full_lock(tp, 0);
12724 tg3_rss_write_indir_tbl(tp);
12725 tg3_full_unlock(tp);
12733 struct tg3 *tp = netdev_priv(dev);
12736 channel->max_rx = tp->rxq_max;
12737 channel->max_tx = tp->txq_max;
12740 channel->rx_count = tp->rxq_cnt;
12741 channel->tx_count = tp->txq_cnt;
12743 if (tp->rxq_req)
12744 channel->rx_count = tp->rxq_req;
12746 channel->rx_count = min(deflt_qs, tp->rxq_max);
12748 if (tp->txq_req)
12749 channel->tx_count = tp->txq_req;
12751 channel->tx_count = min(deflt_qs, tp->txq_max);
12758 struct tg3 *tp = netdev_priv(dev);
12760 if (!tg3_flag(tp, SUPPORT_MSIX))
12763 if (channel->rx_count > tp->rxq_max ||
12764 channel->tx_count > tp->txq_max)
12767 tp->rxq_req = channel->rx_count;
12768 tp->txq_req = channel->tx_count;
12773 tg3_stop(tp);
12775 tg3_carrier_off(tp);
12777 tg3_start(tp, true, false, false);
12800 struct tg3 *tp = netdev_priv(dev);
12822 tw32(MAC_LED_CTRL, tp->led_ctrl);
12832 struct tg3 *tp = netdev_priv(dev);
12834 if (tp->hw_stats)
12835 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12840 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12847 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12854 if (tg3_nvram_read(tp, offset, &val))
12864 if (tg3_nvram_read(tp, offset + 4, &offset))
12867 offset = tg3_nvram_logical_addr(tp, offset);
12886 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12896 cnt = pci_read_vpd(tp->pdev, pos,
12926 static int tg3_test_nvram(struct tg3 *tp)
12932 if (tg3_flag(tp, NO_NVRAM))
12935 if (tg3_nvram_read(tp, 0, &magic) != 0)
12978 err = tg3_nvram_read_be32(tp, i, &buf[j]);
13069 buf = tg3_vpd_readblock(tp, &len);
13108 static int tg3_test_link(struct tg3 *tp)
13112 if (!netif_running(tp->dev))
13115 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
13121 if (tp->link_up)
13132 static int tg3_test_registers(struct tg3 *tp)
13282 if (tg3_flag(tp, 5705_PLUS)) {
13284 if (tg3_flag(tp, 5750_PLUS))
13295 if (tg3_flag(tp, IS_5788) &&
13345 if (netif_msg_hw(tp))
13346 netdev_err(tp->dev,
13352 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13362 tg3_write_mem(tp, offset + j, test_pattern[i]);
13363 tg3_read_mem(tp, offset + j, &val);
13371 static int tg3_test_memory(struct tg3 *tp)
13418 if (tg3_flag(tp, 5717_PLUS))
13420 else if (tg3_flag(tp, 57765_CLASS) ||
13421 tg3_asic_rev(tp) == ASIC_REV_5762)
13423 else if (tg3_flag(tp, 5755_PLUS))
13425 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13427 else if (tg3_flag(tp, 5705_PLUS))
13433 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13464 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13475 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13477 tnapi = &tp->napi[0];
13478 rnapi = &tp->napi[0];
13479 if (tp->irq_cnt > 1) {
13480 if (tg3_flag(tp, ENABLE_RSS))
13481 rnapi = &tp->napi[1];
13482 if (tg3_flag(tp, ENABLE_TSS))
13483 tnapi = &tp->napi[1];
13490 skb = netdev_alloc_skb(tp->dev, tx_len);
13495 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13519 if (tg3_flag(tp, HW_TSO_1) ||
13520 tg3_flag(tp, HW_TSO_2) ||
13521 tg3_flag(tp, HW_TSO_3)) {
13529 if (tg3_flag(tp, HW_TSO_3)) {
13534 } else if (tg3_flag(tp, HW_TSO_2))
13536 else if (tg3_flag(tp, HW_TSO_1) ||
13537 tg3_asic_rev(tp) == ASIC_REV_5705) {
13548 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13556 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13557 if (pci_dma_mapping_error(tp->pdev, map)) {
13566 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13593 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13655 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13658 rx_data += TG3_RX_OFFSET(tp);
13680 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13686 if (tp->dma_limit)
13687 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13689 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13690 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13692 if (!netif_running(tp->dev)) {
13700 err = tg3_reset_hw(tp, true);
13709 if (tg3_flag(tp, ENABLE_RSS)) {
13723 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13724 !tg3_flag(tp, CPMU_PRESENT)) {
13725 tg3_mac_loopback(tp, true);
13727 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13730 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13731 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13734 tg3_mac_loopback(tp, false);
13737 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13738 !tg3_flag(tp, USE_PHYLIB)) {
13741 tg3_phy_lpbk_set(tp, 0, false);
13750 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13752 if (tg3_flag(tp, TSO_CAPABLE) &&
13753 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13755 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13756 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13760 tg3_phy_lpbk_set(tp, 0, true);
13768 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13771 if (tg3_flag(tp, TSO_CAPABLE) &&
13772 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13775 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13776 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13782 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13783 tg3_phy_toggle_apd(tp, true);
13790 tp->phy_flags |= eee_cap;
13798 struct tg3 *tp = netdev_priv(dev);
13801 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13802 if (tg3_power_up(tp)) {
13807 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13812 if (tg3_test_nvram(tp) != 0) {
13816 if (!doextlpbk && tg3_test_link(tp)) {
13824 tg3_phy_stop(tp);
13825 tg3_netif_stop(tp);
13829 tg3_full_lock(tp, irq_sync);
13830 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13831 err = tg3_nvram_lock(tp);
13832 tg3_halt_cpu(tp, RX_CPU_BASE);
13833 if (!tg3_flag(tp, 5705_PLUS))
13834 tg3_halt_cpu(tp, TX_CPU_BASE);
13836 tg3_nvram_unlock(tp);
13838 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13839 tg3_phy_reset(tp);
13841 if (tg3_test_registers(tp) != 0) {
13846 if (tg3_test_memory(tp) != 0) {
13854 if (tg3_test_loopback(tp, data, doextlpbk))
13857 tg3_full_unlock(tp);
13859 if (tg3_test_interrupt(tp) != 0) {
13864 tg3_full_lock(tp, 0);
13866 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13868 tg3_flag_set(tp, INIT_COMPLETE);
13869 err2 = tg3_restart_hw(tp, true);
13871 tg3_netif_start(tp);
13874 tg3_full_unlock(tp);
13877 tg3_phy_start(tp);
13879 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13880 tg3_power_down_prepare(tp);
13886 struct tg3 *tp = netdev_priv(dev);
13889 if (!tg3_flag(tp, PTP_CAPABLE))
13904 tp->rxptpctl = 0;
13907 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13911 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13915 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13919 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13923 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13927 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13931 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13935 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13939 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13943 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13947 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13951 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13958 if (netif_running(dev) && tp->rxptpctl)
13960 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13963 tg3_flag_set(tp, TX_TSTAMP_EN);
13965 tg3_flag_clear(tp, TX_TSTAMP_EN);
13973 struct tg3 *tp = netdev_priv(dev);
13976 if (!tg3_flag(tp, PTP_CAPABLE))
13980 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13983 switch (tp->rxptpctl) {
14035 struct tg3 *tp = netdev_priv(dev);
14038 if (tg3_flag(tp, USE_PHYLIB)) {
14040 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
14042 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
14048 data->phy_id = tp->phy_addr;
14054 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14060 spin_lock_bh(&tp->lock);
14061 err = __tg3_readphy(tp, data->phy_id & 0x1f,
14063 spin_unlock_bh(&tp->lock);
14071 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14077 spin_lock_bh(&tp->lock);
14078 err = __tg3_writephy(tp, data->phy_id & 0x1f,
14080 spin_unlock_bh(&tp->lock);
14099 struct tg3 *tp = netdev_priv(dev);
14101 memcpy(ec, &tp->coal, sizeof(*ec));
14107 struct tg3 *tp = netdev_priv(dev);
14111 if (!tg3_flag(tp, 5705_PLUS)) {
14133 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14134 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14135 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14136 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14137 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14138 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14139 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14140 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14141 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14144 tg3_full_lock(tp, 0);
14145 __tg3_set_coalesce(tp, &tp->coal);
14146 tg3_full_unlock(tp);
14153 struct tg3 *tp = netdev_priv(dev);
14155 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14156 netdev_warn(tp->dev, "Board does not support EEE!\n");
14160 if (edata->advertised != tp->eee.advertised) {
14161 netdev_warn(tp->dev,
14167 netdev_warn(tp->dev,
14173 tp->eee = *edata;
14175 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14176 tg3_warn_mgmt_link_flap(tp);
14178 if (netif_running(tp->dev)) {
14179 tg3_full_lock(tp, 0);
14180 tg3_setup_eee(tp);
14181 tg3_phy_reset(tp);
14182 tg3_full_unlock(tp);
14190 struct tg3 *tp = netdev_priv(dev);
14192 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14193 netdev_warn(tp->dev,
14198 *edata = tp->eee;
14247 struct tg3 *tp = netdev_priv(dev);
14249 spin_lock_bh(&tp->lock);
14250 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) {
14251 *stats = tp->net_stats_prev;
14252 spin_unlock_bh(&tp->lock);
14256 tg3_get_nstats(tp, stats);
14257 spin_unlock_bh(&tp->lock);
14262 struct tg3 *tp = netdev_priv(dev);
14267 tg3_full_lock(tp, 0);
14269 tg3_full_unlock(tp);
14272 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14278 if (tg3_flag(tp, 5780_CLASS)) {
14280 tg3_flag_clear(tp, TSO_CAPABLE);
14282 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14285 if (tg3_flag(tp, 5780_CLASS)) {
14286 tg3_flag_set(tp, TSO_CAPABLE);
14289 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14295 struct tg3 *tp = netdev_priv(dev);
14303 tg3_set_mtu(dev, tp, new_mtu);
14307 tg3_phy_stop(tp);
14309 tg3_netif_stop(tp);
14311 tg3_set_mtu(dev, tp, new_mtu);
14313 tg3_full_lock(tp, 1);
14315 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14320 if (tg3_asic_rev(tp) == ASIC_REV_57766 ||
14321 tg3_asic_rev(tp) == ASIC_REV_5717 ||
14322 tg3_asic_rev(tp) == ASIC_REV_5719 ||
14323 tg3_asic_rev(tp) == ASIC_REV_5720)
14326 err = tg3_restart_hw(tp, reset_phy);
14329 tg3_netif_start(tp);
14331 tg3_full_unlock(tp);
14334 tg3_phy_start(tp);
14357 static void tg3_get_eeprom_size(struct tg3 *tp)
14361 tp->nvram_size = EEPROM_CHIP_SIZE;
14363 if (tg3_nvram_read(tp, 0, &magic) != 0)
14378 while (cursize < tp->nvram_size) {
14379 if (tg3_nvram_read(tp, cursize, &val) != 0)
14388 tp->nvram_size = cursize;
14391 static void tg3_get_nvram_size(struct tg3 *tp)
14395 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14400 tg3_get_eeprom_size(tp);
14404 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14417 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14421 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14424 static void tg3_get_nvram_info(struct tg3 *tp)
14430 tg3_flag_set(tp, FLASH);
14436 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14437 tg3_flag(tp, 5780_CLASS)) {
14440 tp->nvram_jedecnum = JEDEC_ATMEL;
14441 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14442 tg3_flag_set(tp, NVRAM_BUFFERED);
14445 tp->nvram_jedecnum = JEDEC_ATMEL;
14446 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14449 tp->nvram_jedecnum = JEDEC_ATMEL;
14450 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14451 tg3_flag_set(tp, NVRAM_BUFFERED);
14454 tp->nvram_jedecnum = JEDEC_ST;
14455 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14456 tg3_flag_set(tp, NVRAM_BUFFERED);
14459 tp->nvram_jedecnum = JEDEC_SAIFUN;
14460 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14464 tp->nvram_jedecnum = JEDEC_SST;
14465 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14469 tp->nvram_jedecnum = JEDEC_ATMEL;
14470 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14471 tg3_flag_set(tp, NVRAM_BUFFERED);
14475 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14479 tp->nvram_pagesize = 256;
14482 tp->nvram_pagesize = 512;
14485 tp->nvram_pagesize = 1024;
14488 tp->nvram_pagesize = 2048;
14491 tp->nvram_pagesize = 4096;
14494 tp->nvram_pagesize = 264;
14497 tp->nvram_pagesize = 528;
14502 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14510 tg3_flag_set(tp, PROTECTED_NVRAM);
14515 tp->nvram_jedecnum = JEDEC_ATMEL;
14516 tg3_flag_set(tp, NVRAM_BUFFERED);
14519 tp->nvram_jedecnum = JEDEC_ATMEL;
14520 tg3_flag_set(tp, NVRAM_BUFFERED);
14521 tg3_flag_set(tp, FLASH);
14526 tp->nvram_jedecnum = JEDEC_ST;
14527 tg3_flag_set(tp, NVRAM_BUFFERED);
14528 tg3_flag_set(tp, FLASH);
14532 if (tg3_flag(tp, FLASH)) {
14533 tg3_nvram_get_pagesize(tp, nvcfg1);
14536 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14543 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14551 tg3_flag_set(tp, PROTECTED_NVRAM);
14561 tp->nvram_jedecnum = JEDEC_ATMEL;
14562 tg3_flag_set(tp, NVRAM_BUFFERED);
14563 tg3_flag_set(tp, FLASH);
14564 tp->nvram_pagesize = 264;
14567 tp->nvram_size = (protect ? 0x3e200 :
14570 tp->nvram_size = (protect ? 0x1f200 :
14573 tp->nvram_size = (protect ? 0x1f200 :
14579 tp->nvram_jedecnum = JEDEC_ST;
14580 tg3_flag_set(tp, NVRAM_BUFFERED);
14581 tg3_flag_set(tp, FLASH);
14582 tp->nvram_pagesize = 256;
14584 tp->nvram_size = (protect ?
14588 tp->nvram_size = (protect ?
14592 tp->nvram_size = (protect ?
14599 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14610 tp->nvram_jedecnum = JEDEC_ATMEL;
14611 tg3_flag_set(tp, NVRAM_BUFFERED);
14612 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14621 tp->nvram_jedecnum = JEDEC_ATMEL;
14622 tg3_flag_set(tp, NVRAM_BUFFERED);
14623 tg3_flag_set(tp, FLASH);
14624 tp->nvram_pagesize = 264;
14629 tp->nvram_jedecnum = JEDEC_ST;
14630 tg3_flag_set(tp, NVRAM_BUFFERED);
14631 tg3_flag_set(tp, FLASH);
14632 tp->nvram_pagesize = 256;
14637 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14645 tg3_flag_set(tp, PROTECTED_NVRAM);
14659 tp->nvram_jedecnum = JEDEC_ATMEL;
14660 tg3_flag_set(tp, NVRAM_BUFFERED);
14661 tg3_flag_set(tp, FLASH);
14662 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14663 tp->nvram_pagesize = 256;
14673 tp->nvram_jedecnum = JEDEC_ST;
14674 tg3_flag_set(tp, NVRAM_BUFFERED);
14675 tg3_flag_set(tp, FLASH);
14676 tp->nvram_pagesize = 256;
14681 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14688 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14694 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14700 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14706 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14712 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14714 tp->nvram_jedecnum = JEDEC_ATMEL;
14715 tg3_flag_set(tp, NVRAM_BUFFERED);
14716 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14719 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14728 tp->nvram_jedecnum = JEDEC_ATMEL;
14729 tg3_flag_set(tp, NVRAM_BUFFERED);
14730 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14742 tp->nvram_jedecnum = JEDEC_ATMEL;
14743 tg3_flag_set(tp, NVRAM_BUFFERED);
14744 tg3_flag_set(tp, FLASH);
14750 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14754 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14758 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14765 tp->nvram_jedecnum = JEDEC_ST;
14766 tg3_flag_set(tp, NVRAM_BUFFERED);
14767 tg3_flag_set(tp, FLASH);
14771 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14774 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14777 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14782 tg3_flag_set(tp, NO_NVRAM);
14786 tg3_nvram_get_pagesize(tp, nvcfg1);
14787 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14788 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14792 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14801 tp->nvram_jedecnum = JEDEC_ATMEL;
14802 tg3_flag_set(tp, NVRAM_BUFFERED);
14803 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14815 tp->nvram_jedecnum = JEDEC_ATMEL;
14816 tg3_flag_set(tp, NVRAM_BUFFERED);
14817 tg3_flag_set(tp, FLASH);
14825 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14828 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14842 tp->nvram_jedecnum = JEDEC_ST;
14843 tg3_flag_set(tp, NVRAM_BUFFERED);
14844 tg3_flag_set(tp, FLASH);
14853 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14856 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14861 tg3_flag_set(tp, NO_NVRAM);
14865 tg3_nvram_get_pagesize(tp, nvcfg1);
14866 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14867 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14870 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14877 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14879 tg3_flag_set(tp, NO_NVRAM);
14889 tp->nvram_pagesize = 4096;
14890 tp->nvram_jedecnum = JEDEC_MACRONIX;
14891 tg3_flag_set(tp, NVRAM_BUFFERED);
14892 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14893 tg3_flag_set(tp, FLASH);
14895 tp->nvram_size =
14919 tp->nvram_jedecnum = JEDEC_ATMEL;
14920 tg3_flag_set(tp, NVRAM_BUFFERED);
14925 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14927 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14941 tp->nvram_jedecnum = JEDEC_ATMEL;
14942 tg3_flag_set(tp, NVRAM_BUFFERED);
14943 tg3_flag_set(tp, FLASH);
14949 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14954 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14958 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14961 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14962 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14984 tp->nvram_jedecnum = JEDEC_ST;
14985 tg3_flag_set(tp, NVRAM_BUFFERED);
14986 tg3_flag_set(tp, FLASH);
14993 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14999 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
15005 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
15008 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15009 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
15014 tg3_flag_set(tp, NO_NVRAM);
15018 tg3_nvram_get_pagesize(tp, nvcfg1);
15019 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
15020 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
15022 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
15025 if (tg3_nvram_read(tp, 0, &val))
15030 tg3_flag_set(tp, NO_NVRAM);
15035 static void tg3_nvram_init(struct tg3 *tp)
15037 if (tg3_flag(tp, IS_SSB_CORE)) {
15039 tg3_flag_clear(tp, NVRAM);
15040 tg3_flag_clear(tp, NVRAM_BUFFERED);
15041 tg3_flag_set(tp, NO_NVRAM);
15057 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15058 tg3_asic_rev(tp) != ASIC_REV_5701) {
15059 tg3_flag_set(tp, NVRAM);
15061 if (tg3_nvram_lock(tp)) {
15062 netdev_warn(tp->dev,
15067 tg3_enable_nvram_access(tp);
15069 tp->nvram_size = 0;
15071 if (tg3_asic_rev(tp) == ASIC_REV_5752)
15072 tg3_get_5752_nvram_info(tp);
15073 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
15074 tg3_get_5755_nvram_info(tp);
15075 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
15076 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15077 tg3_asic_rev(tp) == ASIC_REV_5785)
15078 tg3_get_5787_nvram_info(tp);
15079 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
15080 tg3_get_5761_nvram_info(tp);
15081 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
15082 tg3_get_5906_nvram_info(tp);
15083 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
15084 tg3_flag(tp, 57765_CLASS))
15085 tg3_get_57780_nvram_info(tp);
15086 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15087 tg3_asic_rev(tp) == ASIC_REV_5719)
15088 tg3_get_5717_nvram_info(tp);
15089 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
15090 tg3_asic_rev(tp) == ASIC_REV_5762)
15091 tg3_get_5720_nvram_info(tp);
15093 tg3_get_nvram_info(tp);
15095 if (tp->nvram_size == 0)
15096 tg3_get_nvram_size(tp);
15098 tg3_disable_nvram_access(tp);
15099 tg3_nvram_unlock(tp);
15102 tg3_flag_clear(tp, NVRAM);
15103 tg3_flag_clear(tp, NVRAM_BUFFERED);
15105 tg3_get_eeprom_size(tp);
15178 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
15184 tp->pdev->subsystem_vendor) &&
15186 tp->pdev->subsystem_device))
15192 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
15196 tp->phy_id = TG3_PHY_ID_INVALID;
15197 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15200 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15201 tg3_flag_set(tp, WOL_CAP);
15203 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15205 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15206 tg3_flag_set(tp, IS_NIC);
15210 tg3_flag_set(tp, ASPM_WORKAROUND);
15213 tg3_flag_set(tp, WOL_ENABLE);
15214 device_set_wakeup_enable(&tp->pdev->dev, true);
15219 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15226 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15227 tp->nic_sram_data_cfg = nic_cfg;
15229 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15231 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15232 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15233 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15235 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15237 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15238 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15240 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15241 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15242 tg3_asic_rev(tp) == ASIC_REV_5720)
15243 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15249 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15260 tp->phy_id = eeprom_phy_id;
15262 if (!tg3_flag(tp, 5705_PLUS))
15263 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15265 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15268 if (tg3_flag(tp, 5750_PLUS))
15277 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15281 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15285 tp->led_ctrl = LED_CTRL_MODE_MAC;
15290 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15291 tg3_asic_rev(tp) == ASIC_REV_5701)
15292 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15297 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15298 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15299 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15300 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15303 if (tg3_flag(tp, 5717_PLUS) ||
15304 tg3_asic_rev(tp) == ASIC_REV_5762)
15305 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15311 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15315 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15316 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15317 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15323 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15324 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15325 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15326 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15328 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15329 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15332 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15333 if ((tp->pdev->subsystem_vendor ==
15335 (tp->pdev->subsystem_device == 0x205a ||
15336 tp->pdev->subsystem_device == 0x2063))
15337 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15339 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15340 tg3_flag_set(tp, IS_NIC);
15344 tg3_flag_set(tp, ENABLE_ASF);
15345 if (tg3_flag(tp, 5750_PLUS))
15346 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15350 tg3_flag(tp, 5750_PLUS))
15351 tg3_flag_set(tp, ENABLE_APE);
15353 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15355 tg3_flag_clear(tp, WOL_CAP);
15357 if (tg3_flag(tp, WOL_CAP) &&
15359 tg3_flag_set(tp, WOL_ENABLE);
15360 device_set_wakeup_enable(&tp->pdev->dev, true);
15364 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15369 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15371 if ((tg3_flag(tp, 57765_PLUS) ||
15372 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15373 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15375 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15377 if (tg3_flag(tp, PCI_EXPRESS)) {
15380 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15381 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15382 !tg3_flag(tp, 57765_PLUS) &&
15384 tg3_flag_set(tp, ASPM_WORKAROUND);
15386 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15388 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15392 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15394 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15396 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15399 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15402 if (tg3_flag(tp, WOL_CAP))
15403 device_set_wakeup_enable(&tp->pdev->dev,
15404 tg3_flag(tp, WOL_ENABLE));
15406 device_set_wakeup_capable(&tp->pdev->dev, false);
15409 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15414 err = tg3_nvram_lock(tp);
15418 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15419 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15421 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15425 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15427 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15433 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15435 tg3_nvram_unlock(tp);
15442 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15465 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15471 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15476 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15483 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15491 static void tg3_phy_init_link_config(struct tg3 *tp)
15495 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15496 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15501 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15510 tp->link_config.advertising = adv;
15511 tp->link_config.speed = SPEED_UNKNOWN;
15512 tp->link_config.duplex = DUPLEX_UNKNOWN;
15513 tp->link_config.autoneg = AUTONEG_ENABLE;
15514 tp->link_config.active_speed = SPEED_UNKNOWN;
15515 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15517 tp->old_link = -1;
15520 static int tg3_phy_probe(struct tg3 *tp)
15527 tg3_flag_set(tp, PAUSE_AUTONEG);
15528 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15530 if (tg3_flag(tp, ENABLE_APE)) {
15531 switch (tp->pci_fn) {
15533 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15536 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15539 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15542 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15547 if (!tg3_flag(tp, ENABLE_ASF) &&
15548 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15549 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15550 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15553 if (tg3_flag(tp, USE_PHYLIB))
15554 return tg3_phy_init(tp);
15560 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15568 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15569 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15579 tp->phy_id = hw_phy_id;
15581 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15583 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15585 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15595 p = tg3_lookup_by_subsys(tp);
15597 tp->phy_id = p->phy_id;
15598 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15609 if (!tp->phy_id ||
15610 tp->phy_id == TG3_PHY_ID_BCM8002)
15611 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15615 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15616 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15617 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15618 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15619 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15620 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15621 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15622 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15623 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15624 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15626 tp->eee.supported = SUPPORTED_100baseT_Full |
15628 tp->eee.advertised = ADVERTISED_100baseT_Full |
15630 tp->eee.eee_enabled = 1;
15631 tp->eee.tx_lpi_enabled = 1;
15632 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15635 tg3_phy_init_link_config(tp);
15637 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15638 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15639 !tg3_flag(tp, ENABLE_APE) &&
15640 !tg3_flag(tp, ENABLE_ASF)) {
15643 tg3_readphy(tp, MII_BMSR, &bmsr);
15644 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15648 err = tg3_phy_reset(tp);
15652 tg3_phy_set_wirespeed(tp);
15654 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15655 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15656 tp->link_config.flowctrl);
15658 tg3_writephy(tp, MII_BMCR,
15664 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15665 err = tg3_init_5401phy_dsp(tp);
15669 err = tg3_init_5401phy_dsp(tp);
15675 static void tg3_read_vpd(struct tg3 *tp)
15682 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15718 if (len >= sizeof(tp->fw_ver))
15719 len = sizeof(tp->fw_ver) - 1;
15720 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15721 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15738 memcpy(tp->board_part_number, &vpd_data[i], len);
15742 if (tp->board_part_number[0])
15746 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15747 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15748 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15749 strcpy(tp->board_part_number, "BCM5717");
15750 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15751 strcpy(tp->board_part_number, "BCM5718");
15754 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15755 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15756 strcpy(tp->board_part_number, "BCM57780");
15757 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15758 strcpy(tp->board_part_number, "BCM57760");
15759 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15760 strcpy(tp->board_part_number, "BCM57790");
15761 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15762 strcpy(tp->board_part_number, "BCM57788");
15765 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15766 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15767 strcpy(tp->board_part_number, "BCM57761");
15768 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15769 strcpy(tp->board_part_number, "BCM57765");
15770 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15771 strcpy(tp->board_part_number, "BCM57781");
15772 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15773 strcpy(tp->board_part_number, "BCM57785");
15774 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15775 strcpy(tp->board_part_number, "BCM57791");
15776 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15777 strcpy(tp->board_part_number, "BCM57795");
15780 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15781 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15782 strcpy(tp->board_part_number, "BCM57762");
15783 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15784 strcpy(tp->board_part_number, "BCM57766");
15785 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15786 strcpy(tp->board_part_number, "BCM57782");
15787 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15788 strcpy(tp->board_part_number, "BCM57786");
15791 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15792 strcpy(tp->board_part_number, "BCM95906");
15795 strcpy(tp->board_part_number, "none");
15799 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15803 if (tg3_nvram_read(tp, offset, &val) ||
15805 tg3_nvram_read(tp, offset + 4, &val) ||
15812 static void tg3_read_bc_ver(struct tg3 *tp)
15818 if (tg3_nvram_read(tp, 0xc, &offset) ||
15819 tg3_nvram_read(tp, 0x4, &start))
15822 offset = tg3_nvram_logical_addr(tp, offset);
15824 if (tg3_nvram_read(tp, offset, &val))
15828 if (tg3_nvram_read(tp, offset + 4, &val))
15835 dst_off = strlen(tp->fw_ver);
15839 tg3_nvram_read(tp, offset + 8, &ver_offset))
15845 if (tg3_nvram_read_be32(tp, offset + i, &v))
15848 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15853 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15859 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15864 static void tg3_read_hwsb_ver(struct tg3 *tp)
15869 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15877 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15880 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15884 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15912 if (tg3_nvram_read(tp, offset, &val))
15924 offset = strlen(tp->fw_ver);
15925 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15929 offset = strlen(tp->fw_ver);
15931 tp->fw_ver[offset] = 'a' + build - 1;
15935 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15943 if (tg3_nvram_read(tp, offset, &val))
15953 if (!tg3_flag(tp, 5705_PLUS))
15955 else if (tg3_nvram_read(tp, offset - 4, &start))
15958 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15959 !tg3_fw_img_is_valid(tp, offset) ||
15960 tg3_nvram_read(tp, offset + 8, &val))
15965 vlen = strlen(tp->fw_ver);
15967 tp->fw_ver[vlen++] = ',';
15968 tp->fw_ver[vlen++] = ' ';
15972 if (tg3_nvram_read_be32(tp, offset, &v))
15978 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15982 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15987 static void tg3_probe_ncsi(struct tg3 *tp)
15991 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15995 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15999 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
16000 tg3_flag_set(tp, APE_HAS_NCSI);
16003 static void tg3_read_dash_ver(struct tg3 *tp)
16009 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
16011 if (tg3_flag(tp, APE_HAS_NCSI))
16013 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
16018 vlen = strlen(tp->fw_ver);
16020 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
16028 static void tg3_read_otp_ver(struct tg3 *tp)
16032 if (tg3_asic_rev(tp) != ASIC_REV_5762)
16035 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
16036 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
16048 vlen = strlen(tp->fw_ver);
16049 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
16053 static void tg3_read_fw_ver(struct tg3 *tp)
16058 if (tp->fw_ver[0] != 0)
16061 if (tg3_flag(tp, NO_NVRAM)) {
16062 strcat(tp->fw_ver, "sb");
16063 tg3_read_otp_ver(tp);
16067 if (tg3_nvram_read(tp, 0, &val))
16071 tg3_read_bc_ver(tp);
16073 tg3_read_sb_ver(tp, val);
16075 tg3_read_hwsb_ver(tp);
16077 if (tg3_flag(tp, ENABLE_ASF)) {
16078 if (tg3_flag(tp, ENABLE_APE)) {
16079 tg3_probe_ncsi(tp);
16081 tg3_read_dash_ver(tp);
16083 tg3_read_mgmtfw_ver(tp);
16087 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
16090 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
16092 if (tg3_flag(tp, LRG_PROD_RING_CAP))
16094 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
16107 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16110 unsigned int func, devnr = tp->pdev->devfn & ~7;
16113 peer = pci_get_slot(tp->pdev->bus, devnr | func);
16114 if (peer && peer != tp->pdev)
16119 * tp->pdev in that case.
16122 peer = tp->pdev;
16135 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
16137 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
16138 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
16144 tg3_flag_set(tp, CPMU_PRESENT);
16146 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
16147 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
16148 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16149 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
16150 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
16151 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16152 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
16153 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16154 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
16155 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16156 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
16158 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16159 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16160 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16161 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16162 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16163 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16164 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16165 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16166 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16167 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16172 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16178 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
16179 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16181 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
16182 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16184 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16185 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16186 tg3_asic_rev(tp) == ASIC_REV_5720)
16187 tg3_flag_set(tp, 5717_PLUS);
16189 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16190 tg3_asic_rev(tp) == ASIC_REV_57766)
16191 tg3_flag_set(tp, 57765_CLASS);
16193 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
16194 tg3_asic_rev(tp) == ASIC_REV_5762)
16195 tg3_flag_set(tp, 57765_PLUS);
16198 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16199 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16200 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16201 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16202 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16203 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16204 tg3_flag(tp, 57765_PLUS))
16205 tg3_flag_set(tp, 5755_PLUS);
16207 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16208 tg3_asic_rev(tp) == ASIC_REV_5714)
16209 tg3_flag_set(tp, 5780_CLASS);
16211 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16212 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16213 tg3_asic_rev(tp) == ASIC_REV_5906 ||
16214 tg3_flag(tp, 5755_PLUS) ||
16215 tg3_flag(tp, 5780_CLASS))
16216 tg3_flag_set(tp, 5750_PLUS);
16218 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16219 tg3_flag(tp, 5750_PLUS))
16220 tg3_flag_set(tp, 5705_PLUS);
16223 static bool tg3_10_100_only_device(struct tg3 *tp,
16228 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16230 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16234 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16245 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16260 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16262 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16269 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16271 tp->misc_host_ctrl |= (misc_ctrl_reg &
16273 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16274 tp->misc_host_ctrl);
16276 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16295 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16296 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16328 tp->pdev->bus->number)) {
16329 tg3_flag_set(tp, ICH_WORKAROUND);
16336 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16358 tp->pdev->bus->number) &&
16360 tp->pdev->bus->number)) {
16361 tg3_flag_set(tp, 5701_DMA_BUG);
16374 if (tg3_flag(tp, 5780_CLASS)) {
16375 tg3_flag_set(tp, 40BIT_DMA_BUG);
16376 tp->msi_cap = tp->pdev->msi_cap;
16386 tp->pdev->bus->number) &&
16388 tp->pdev->bus->number)) {
16389 tg3_flag_set(tp, 40BIT_DMA_BUG);
16396 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16397 tg3_asic_rev(tp) == ASIC_REV_5714)
16398 tp->pdev_peer = tg3_find_peer(tp);
16401 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16403 else if (tg3_flag(tp, 57765_PLUS))
16404 tg3_flag_set(tp, HW_TSO_3);
16405 else if (tg3_flag(tp, 5755_PLUS) ||
16406 tg3_asic_rev(tp) == ASIC_REV_5906)
16407 tg3_flag_set(tp, HW_TSO_2);
16408 else if (tg3_flag(tp, 5750_PLUS)) {
16409 tg3_flag_set(tp, HW_TSO_1);
16410 tg3_flag_set(tp, TSO_BUG);
16411 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16412 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16413 tg3_flag_clear(tp, TSO_BUG);
16414 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16415 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16416 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16417 tg3_flag_set(tp, FW_TSO);
16418 tg3_flag_set(tp, TSO_BUG);
16419 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16420 tp->fw_needed = FIRMWARE_TG3TSO5;
16422 tp->fw_needed = FIRMWARE_TG3TSO;
16426 if (tg3_flag(tp, HW_TSO_1) ||
16427 tg3_flag(tp, HW_TSO_2) ||
16428 tg3_flag(tp, HW_TSO_3) ||
16429 tg3_flag(tp, FW_TSO)) {
16434 tg3_flag_set(tp, TSO_CAPABLE);
16436 tg3_flag_clear(tp, TSO_CAPABLE);
16437 tg3_flag_clear(tp, TSO_BUG);
16438 tp->fw_needed = NULL;
16441 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16442 tp->fw_needed = FIRMWARE_TG3;
16444 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16445 tp->fw_needed = FIRMWARE_TG357766;
16447 tp->irq_max = 1;
16449 if (tg3_flag(tp, 5750_PLUS)) {
16450 tg3_flag_set(tp, SUPPORT_MSI);
16451 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16452 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16453 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16454 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16455 tp->pdev_peer == tp->pdev))
16456 tg3_flag_clear(tp, SUPPORT_MSI);
16458 if (tg3_flag(tp, 5755_PLUS) ||
16459 tg3_asic_rev(tp) == ASIC_REV_5906) {
16460 tg3_flag_set(tp, 1SHOT_MSI);
16463 if (tg3_flag(tp, 57765_PLUS)) {
16464 tg3_flag_set(tp, SUPPORT_MSIX);
16465 tp->irq_max = TG3_IRQ_MAX_VECS;
16469 tp->txq_max = 1;
16470 tp->rxq_max = 1;
16471 if (tp->irq_max > 1) {
16472 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16473 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16475 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16476 tg3_asic_rev(tp) == ASIC_REV_5720)
16477 tp->txq_max = tp->irq_max - 1;
16480 if (tg3_flag(tp, 5755_PLUS) ||
16481 tg3_asic_rev(tp) == ASIC_REV_5906)
16482 tg3_flag_set(tp, SHORT_DMA_BUG);
16484 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16485 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16487 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16488 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16489 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16490 tg3_asic_rev(tp) == ASIC_REV_5762)
16491 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16493 if (tg3_flag(tp, 57765_PLUS) &&
16494 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16495 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16497 if (!tg3_flag(tp, 5705_PLUS) ||
16498 tg3_flag(tp, 5780_CLASS) ||
16499 tg3_flag(tp, USE_JUMBO_BDFLAG))
16500 tg3_flag_set(tp, JUMBO_CAPABLE);
16502 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16505 if (pci_is_pcie(tp->pdev)) {
16508 tg3_flag_set(tp, PCI_EXPRESS);
16510 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16512 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16513 tg3_flag_clear(tp, HW_TSO_2);
16514 tg3_flag_clear(tp, TSO_CAPABLE);
16516 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16517 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16518 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16519 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16520 tg3_flag_set(tp, CLKREQ_BUG);
16521 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16522 tg3_flag_set(tp, L1PLLPD_EN);
16524 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16529 tg3_flag_set(tp, PCI_EXPRESS);
16530 } else if (!tg3_flag(tp, 5705_PLUS) ||
16531 tg3_flag(tp, 5780_CLASS)) {
16532 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16533 if (!tp->pcix_cap) {
16534 dev_err(&tp->pdev->dev,
16540 tg3_flag_set(tp, PCIX_MODE);
16550 !tg3_flag(tp, PCI_EXPRESS))
16551 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16553 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16554 &tp->pci_cacheline_sz);
16555 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16556 &tp->pci_lat_timer);
16557 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16558 tp->pci_lat_timer < 64) {
16559 tp->pci_lat_timer = 64;
16560 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16561 tp->pci_lat_timer);
16567 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16571 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16578 if (tg3_flag(tp, PCIX_MODE)) {
16581 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16587 pci_read_config_dword(tp->pdev,
16588 tp->pdev->pm_cap + PCI_PM_CTRL,
16592 pci_write_config_dword(tp->pdev,
16593 tp->pdev->pm_cap + PCI_PM_CTRL,
16597 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16599 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16604 tg3_flag_set(tp, PCI_HIGH_SPEED);
16606 tg3_flag_set(tp, PCI_32BIT);
16609 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16612 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16616 tp->read32 = tg3_read32;
16617 tp->write32 = tg3_write32;
16618 tp->read32_mbox = tg3_read32;
16619 tp->write32_mbox = tg3_write32;
16620 tp->write32_tx_mbox = tg3_write32;
16621 tp->write32_rx_mbox = tg3_write32;
16624 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16625 tp->write32 = tg3_write_indirect_reg32;
16626 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16627 (tg3_flag(tp, PCI_EXPRESS) &&
16628 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16636 tp->write32 = tg3_write_flush_reg32;
16639 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16640 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16641 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16642 tp->write32_rx_mbox = tg3_write_flush_reg32;
16645 if (tg3_flag(tp, ICH_WORKAROUND)) {
16646 tp->read32 = tg3_read_indirect_reg32;
16647 tp->write32 = tg3_write_indirect_reg32;
16648 tp->read32_mbox = tg3_read_indirect_mbox;
16649 tp->write32_mbox = tg3_write_indirect_mbox;
16650 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16651 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16653 iounmap(tp->regs);
16654 tp->regs = NULL;
16656 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16658 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16660 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16661 tp->read32_mbox = tg3_read32_mbox_5906;
16662 tp->write32_mbox = tg3_write32_mbox_5906;
16663 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16664 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16667 if (tp->write32 == tg3_write_indirect_reg32 ||
16668 (tg3_flag(tp, PCIX_MODE) &&
16669 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16670 tg3_asic_rev(tp) == ASIC_REV_5701)))
16671 tg3_flag_set(tp, SRAM_USE_CONFIG);
16681 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16682 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16683 tg3_flag(tp, 5780_CLASS)) {
16684 if (tg3_flag(tp, PCIX_MODE)) {
16685 pci_read_config_dword(tp->pdev,
16686 tp->pcix_cap + PCI_X_STATUS,
16688 tp->pci_fn = val & 0x7;
16690 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16691 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16692 tg3_asic_rev(tp) == ASIC_REV_5720) {
16693 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16697 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16698 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16700 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16704 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16705 tp->write32_tx_mbox = tg3_write_flush_reg32;
16706 tp->write32_rx_mbox = tg3_write_flush_reg32;
16717 tg3_get_eeprom_hw_cfg(tp);
16719 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16720 tg3_flag_clear(tp, TSO_CAPABLE);
16721 tg3_flag_clear(tp, TSO_BUG);
16722 tp->fw_needed = NULL;
16725 if (tg3_flag(tp, ENABLE_APE)) {
16732 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16735 tg3_ape_lock_init(tp);
16736 tp->ape_hb_interval =
16740 /* Set up tp->grc_local_ctrl before calling
16745 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16746 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16747 tg3_flag(tp, EEPROM_WRITE_PROT))
16748 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16753 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16754 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16756 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16757 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16758 tg3_flag(tp, 57765_CLASS))
16759 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16761 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16762 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16764 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16765 if (tg3_flag(tp, IS_NIC))
16767 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16771 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16772 tp->grc_local_ctrl |=
16776 tg3_pwrsrc_switch_to_vmain(tp);
16781 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16782 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16785 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16786 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16787 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16788 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16789 tg3_flag_clear(tp, WOL_SPEED_100MB);
16791 tg3_flag_set(tp, WOL_SPEED_100MB);
16794 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16795 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16798 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16799 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16800 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16801 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16802 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16803 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16804 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16806 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16807 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16808 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16809 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16810 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16812 if (tg3_flag(tp, 5705_PLUS) &&
16813 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16814 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16815 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16816 !tg3_flag(tp, 57765_PLUS)) {
16817 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16818 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16819 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16820 tg3_asic_rev(tp) == ASIC_REV_5761) {
16821 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16822 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16823 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16824 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16825 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16827 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16830 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16831 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16832 tp->phy_otp = tg3_read_otp_phycfg(tp);
16833 if (tp->phy_otp == 0)
16834 tp->phy_otp = TG3_OTP_DEFAULT;
16837 if (tg3_flag(tp, CPMU_PRESENT))
16838 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16840 tp->mi_mode = MAC_MI_MODE_BASE;
16842 tp->coalesce_mode = 0;
16843 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16844 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16845 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16848 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16849 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16850 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16851 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16852 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16853 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16856 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16857 tg3_asic_rev(tp) == ASIC_REV_57780)
16858 tg3_flag_set(tp, USE_PHYLIB);
16860 err = tg3_mdio_init(tp);
16866 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16867 tg3_asic_rev(tp) == ASIC_REV_5762)
16876 tw32(GRC_MODE, val | tp->grc_mode);
16878 tg3_switch_clocks(tp);
16886 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16889 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16890 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16891 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16892 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16893 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16900 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16906 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16911 tg3_nvram_init(tp);
16914 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16915 !tg3_flag(tp, NO_NVRAM))
16916 tp->fw_needed = NULL;
16921 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16924 tg3_flag_set(tp, IS_5788);
16926 if (!tg3_flag(tp, IS_5788) &&
16927 tg3_asic_rev(tp) != ASIC_REV_5700)
16928 tg3_flag_set(tp, TAGGED_STATUS);
16929 if (tg3_flag(tp, TAGGED_STATUS)) {
16930 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16933 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16934 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16935 tp->misc_host_ctrl);
16939 if (tg3_flag(tp, ENABLE_APE))
16940 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16942 tp->mac_mode = 0;
16944 if (tg3_10_100_only_device(tp, ent))
16945 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16947 err = tg3_phy_probe(tp);
16949 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16951 tg3_mdio_fini(tp);
16954 tg3_read_vpd(tp);
16955 tg3_read_fw_ver(tp);
16957 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16958 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16960 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16961 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16963 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16970 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16971 tg3_flag_set(tp, USE_LINKCHG_REG);
16973 tg3_flag_clear(tp, USE_LINKCHG_REG);
16979 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16980 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16981 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16982 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16983 tg3_flag_set(tp, USE_LINKCHG_REG);
16987 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16988 tg3_flag_set(tp, POLL_SERDES);
16990 tg3_flag_clear(tp, POLL_SERDES);
16992 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16993 tg3_flag_set(tp, POLL_CPMU_LINK);
16995 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16996 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16997 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16998 tg3_flag(tp, PCIX_MODE)) {
16999 tp->rx_offset = NET_SKB_PAD;
17001 tp->rx_copy_thresh = ~(u16)0;
17005 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
17006 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
17007 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
17009 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
17014 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
17015 tg3_asic_rev(tp) == ASIC_REV_5752 ||
17016 tg3_asic_rev(tp) == ASIC_REV_5755)
17017 tp->rx_std_max_post = 8;
17019 if (tg3_flag(tp, ASPM_WORKAROUND))
17020 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
17026 static int tg3_get_device_address(struct tg3 *tp)
17028 struct net_device *dev = tp->dev;
17033 if (!eth_platform_get_mac_address(&tp->pdev->dev, dev->dev_addr))
17036 if (tg3_flag(tp, IS_SSB_CORE)) {
17037 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
17043 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
17044 tg3_flag(tp, 5780_CLASS)) {
17047 if (tg3_nvram_lock(tp))
17050 tg3_nvram_unlock(tp);
17051 } else if (tg3_flag(tp, 5717_PLUS)) {
17052 if (tp->pci_fn & 1)
17054 if (tp->pci_fn > 1)
17056 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
17060 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
17065 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
17076 if (!tg3_flag(tp, NO_NVRAM) &&
17077 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
17078 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
17104 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
17110 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17119 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17120 tg3_asic_rev(tp) != ASIC_REV_5701 &&
17121 !tg3_flag(tp, PCI_EXPRESS))
17134 if (tg3_flag(tp, 57765_PLUS)) {
17153 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
17178 } else if (tg3_flag(tp, PCI_EXPRESS)) {
17245 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17296 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17298 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17300 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17333 static int tg3_test_dma(struct tg3 *tp)
17339 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17346 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17349 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17351 if (tg3_flag(tp, 57765_PLUS))
17354 if (tg3_flag(tp, PCI_EXPRESS)) {
17356 tp->dma_rwctrl |= 0x00180000;
17357 } else if (!tg3_flag(tp, PCIX_MODE)) {
17358 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17359 tg3_asic_rev(tp) == ASIC_REV_5750)
17360 tp->dma_rwctrl |= 0x003f0000;
17362 tp->dma_rwctrl |= 0x003f000f;
17364 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17365 tg3_asic_rev(tp) == ASIC_REV_5704) {
17373 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17374 tg3_asic_rev(tp) == ASIC_REV_5704)
17375 tp->dma_rwctrl |= 0x8000;
17377 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17379 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17382 tp->dma_rwctrl |=
17386 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17388 tp->dma_rwctrl |= 0x00144000;
17389 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17391 tp->dma_rwctrl |= 0x00148000;
17393 tp->dma_rwctrl |= 0x001b000f;
17396 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17397 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17399 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17400 tg3_asic_rev(tp) == ASIC_REV_5704)
17401 tp->dma_rwctrl &= 0xfffffff0;
17403 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17404 tg3_asic_rev(tp) == ASIC_REV_5701) {
17406 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17418 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17421 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17424 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17425 tg3_asic_rev(tp) != ASIC_REV_5701)
17431 saved_dma_rwctrl = tp->dma_rwctrl;
17432 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17433 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17442 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17444 dev_err(&tp->pdev->dev,
17451 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17453 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17463 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17465 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17466 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17467 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17470 dev_err(&tp->pdev->dev,
17484 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17491 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17492 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17495 tp->dma_rwctrl = saved_dma_rwctrl;
17498 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17502 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17507 static void tg3_init_bufmgr_config(struct tg3 *tp)
17509 if (tg3_flag(tp, 57765_PLUS)) {
17510 tp->bufmgr_config.mbuf_read_dma_low_water =
17512 tp->bufmgr_config.mbuf_mac_rx_low_water =
17514 tp->bufmgr_config.mbuf_high_water =
17517 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17519 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17521 tp->bufmgr_config.mbuf_high_water_jumbo =
17523 } else if (tg3_flag(tp, 5705_PLUS)) {
17524 tp->bufmgr_config.mbuf_read_dma_low_water =
17526 tp->bufmgr_config.mbuf_mac_rx_low_water =
17528 tp->bufmgr_config.mbuf_high_water =
17530 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17531 tp->bufmgr_config.mbuf_mac_rx_low_water =
17533 tp->bufmgr_config.mbuf_high_water =
17537 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17539 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17541 tp->bufmgr_config.mbuf_high_water_jumbo =
17544 tp->bufmgr_config.mbuf_read_dma_low_water =
17546 tp->bufmgr_config.mbuf_mac_rx_low_water =
17548 tp->bufmgr_config.mbuf_high_water =
17551 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17553 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17555 tp->bufmgr_config.mbuf_high_water_jumbo =
17559 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17560 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17563 static char *tg3_phy_string(struct tg3 *tp)
17565 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17595 static char *tg3_bus_string(struct tg3 *tp, char *str)
17597 if (tg3_flag(tp, PCI_EXPRESS)) {
17600 } else if (tg3_flag(tp, PCIX_MODE)) {
17619 if (tg3_flag(tp, PCI_HIGH_SPEED))
17624 if (tg3_flag(tp, PCI_32BIT))
17631 static void tg3_init_coal(struct tg3 *tp)
17633 struct ethtool_coalesce *ec = &tp->coal;
17647 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17655 if (tg3_flag(tp, 5705_PLUS)) {
17666 struct tg3 *tp;
17687 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17695 tp = netdev_priv(dev);
17696 tp->pdev = pdev;
17697 tp->dev = dev;
17698 tp->rx_mode = TG3_DEF_RX_MODE;
17699 tp->tx_mode = TG3_DEF_TX_MODE;
17700 tp->irq_sync = 1;
17701 tp->pcierr_recovery = false;
17704 tp->msg_enable = tg3_debug;
17706 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17709 tg3_flag_set(tp, IS_SSB_CORE);
17711 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17713 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17715 tg3_flag_set(tp, USE_PHYLIB);
17716 tg3_flag_set(tp, ROBOSWITCH);
17719 tg3_flag_set(tp, RGMII_MODE);
17726 tp->misc_host_ctrl =
17738 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17741 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17743 spin_lock_init(&tp->lock);
17744 spin_lock_init(&tp->indirect_lock);
17745 INIT_WORK(&tp->reset_task, tg3_reset_task);
17747 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17748 if (!tp->regs) {
17754 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17755 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17756 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17757 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17758 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17759 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17760 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17761 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17762 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17763 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17764 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17765 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17766 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17767 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17768 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17769 tg3_flag_set(tp, ENABLE_APE);
17770 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17771 if (!tp->aperegs) {
17779 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17780 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17787 err = tg3_get_invariants(tp, ent);
17800 if (tg3_flag(tp, IS_5788))
17802 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17833 tg3_init_bufmgr_config(tp);
17838 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17841 if (tg3_flag(tp, 5755_PLUS))
17849 if ((tg3_flag(tp, HW_TSO_1) ||
17850 tg3_flag(tp, HW_TSO_2) ||
17851 tg3_flag(tp, HW_TSO_3)) &&
17854 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17857 if (tg3_flag(tp, HW_TSO_3) ||
17858 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17859 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17860 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17861 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17862 tg3_asic_rev(tp) == ASIC_REV_57780)
17875 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17876 !tg3_flag(tp, CPMU_PRESENT))
17885 dev->max_mtu = TG3_MAX_MTU(tp);
17887 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17888 !tg3_flag(tp, TSO_CAPABLE) &&
17890 tg3_flag_set(tp, MAX_RXPEND_64);
17891 tp->rx_pending = 63;
17894 err = tg3_get_device_address(tp);
17904 for (i = 0; i < tp->irq_max; i++) {
17905 struct tg3_napi *tnapi = &tp->napi[i];
17907 tnapi->tp = tp;
17924 if (!tg3_flag(tp, SUPPORT_MSIX))
17952 tg3_full_lock(tp, 0);
17954 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17955 tg3_full_unlock(tp);
17958 err = tg3_test_dma(tp);
17964 tg3_init_coal(tp);
17968 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17969 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17970 tg3_asic_rev(tp) == ASIC_REV_5762)
17971 tg3_flag_set(tp, PTP_CAPABLE);
17973 tg3_timer_init(tp);
17975 tg3_carrier_off(tp);
17983 if (tg3_flag(tp, PTP_CAPABLE)) {
17984 tg3_ptp_init(tp);
17985 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
17986 &tp->pdev->dev);
17987 if (IS_ERR(tp->ptp_clock))
17988 tp->ptp_clock = NULL;
17992 tp->board_part_number,
17993 tg3_chip_rev_id(tp),
17994 tg3_bus_string(tp, str),
17997 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) {
18000 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
18002 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
18009 tg3_phy_string(tp), ethtype,
18010 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
18011 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
18016 tg3_flag(tp, USE_LINKCHG_REG) != 0,
18017 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
18018 tg3_flag(tp, ENABLE_ASF) != 0,
18019 tg3_flag(tp, TSO_CAPABLE) != 0);
18021 tp->dma_rwctrl,
18030 if (tp->aperegs) {
18031 iounmap(tp->aperegs);
18032 tp->aperegs = NULL;
18036 if (tp->regs) {
18037 iounmap(tp->regs);
18038 tp->regs = NULL;
18058 struct tg3 *tp = netdev_priv(dev);
18060 tg3_ptp_fini(tp);
18062 release_firmware(tp->fw);
18064 tg3_reset_task_cancel(tp);
18066 if (tg3_flag(tp, USE_PHYLIB)) {
18067 tg3_phy_fini(tp);
18068 tg3_mdio_fini(tp);
18072 if (tp->aperegs) {
18073 iounmap(tp->aperegs);
18074 tp->aperegs = NULL;
18076 if (tp->regs) {
18077 iounmap(tp->regs);
18078 tp->regs = NULL;
18090 struct tg3 *tp = netdev_priv(dev);
18098 tg3_reset_task_cancel(tp);
18099 tg3_phy_stop(tp);
18100 tg3_netif_stop(tp);
18102 tg3_timer_stop(tp);
18104 tg3_full_lock(tp, 1);
18105 tg3_disable_ints(tp);
18106 tg3_full_unlock(tp);
18110 tg3_full_lock(tp, 0);
18111 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
18112 tg3_flag_clear(tp, INIT_COMPLETE);
18113 tg3_full_unlock(tp);
18115 err = tg3_power_down_prepare(tp);
18119 tg3_full_lock(tp, 0);
18121 tg3_flag_set(tp, INIT_COMPLETE);
18122 err2 = tg3_restart_hw(tp, true);
18126 tg3_timer_start(tp);
18129 tg3_netif_start(tp);
18132 tg3_full_unlock(tp);
18135 tg3_phy_start(tp);
18146 struct tg3 *tp = netdev_priv(dev);
18156 tg3_full_lock(tp, 0);
18158 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18160 tg3_flag_set(tp, INIT_COMPLETE);
18161 err = tg3_restart_hw(tp,
18162 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
18166 tg3_timer_start(tp);
18168 tg3_netif_start(tp);
18171 tg3_full_unlock(tp);
18174 tg3_phy_start(tp);
18187 struct tg3 *tp = netdev_priv(dev);
18189 tg3_reset_task_cancel(tp);
18199 tg3_power_down(tp);
18218 struct tg3 *tp = netdev_priv(netdev);
18224 tg3_reset_task_cancel(tp);
18229 if (!netdev || tp->pcierr_recovery || !netif_running(netdev))
18234 tp->pcierr_recovery = true;
18236 tg3_phy_stop(tp);
18238 tg3_netif_stop(tp);
18240 tg3_timer_stop(tp);
18245 tg3_full_lock(tp, 0);
18246 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18247 tg3_full_unlock(tp);
18252 tg3_napi_enable(tp);
18277 struct tg3 *tp = netdev_priv(netdev);
18298 err = tg3_power_up(tp);
18306 tg3_napi_enable(tp);
18324 struct tg3 *tp = netdev_priv(netdev);
18332 tg3_full_lock(tp, 0);
18333 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18334 tg3_flag_set(tp, INIT_COMPLETE);
18335 err = tg3_restart_hw(tp, true);
18337 tg3_full_unlock(tp);
18344 tg3_timer_start(tp);
18346 tg3_netif_start(tp);
18348 tg3_full_unlock(tp);
18350 tg3_phy_start(tp);
18353 tp->pcierr_recovery = false;