Lines Matching refs:byte
7734 /* Avoid the 8byte DMA problem */
9222 * Older PCIe devices only support the 128 byte
12069 /* adjustments to start on required 4 byte boundary */
12085 /* read bytes up to the last 4 byte boundary */
12108 /* read last bytes not ending on 4 byte boundary */
12145 /* adjustments to start on required 4 byte boundary */
12157 /* adjustments to end on required 4 byte boundary */
12884 * the byte order as it exists in NVRAM.
16864 /* Initialize data/descriptor byte/word swapping. */
17107 u8 byte;
17110 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17111 if (byte == 0)
17114 cacheline_size = (int) byte * 4;
17410 * to streamable DMA memory with not all the byte
17722 /* The word/byte swap controls here control register access byte
17723 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17732 /* The NONFRM (non-frame) byte/word swap controls take effect