Lines Matching defs:tw32_f
620 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
640 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
641 tw32_f(TG3PCI_MEM_WIN_DATA, val);
644 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
667 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
671 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
1124 tw32_f(MAC_MI_MODE,
1139 tw32_f(MAC_MI_COM, frame_val);
1161 tw32_f(MAC_MI_MODE, tp->mi_mode);
1187 tw32_f(MAC_MI_MODE,
1201 tw32_f(MAC_MI_COM, frame_val);
1220 tw32_f(MAC_MI_MODE, tp->mi_mode);
1495 tw32_f(MAC_MI_MODE, tp->mi_mode);
1626 tw32_f(GRC_RX_CPU_EVENT, val);
1994 tw32_f(MAC_RX_MODE, tp->rx_mode);
2002 tw32_f(MAC_TX_MODE, tp->tx_mode);
2049 tw32_f(MAC_MODE, tp->mac_mode);
2641 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2690 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3084 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3129 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3165 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3537 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3574 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3610 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3626 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3773 tw32_f(cpu_base + CPU_PC, pc);
3780 tw32_f(cpu_base + CPU_PC, pc);
4182 tw32_f(MAC_MODE, mac_mode);
4185 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4735 tw32_f(MAC_STATUS,
4752 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4754 tw32_f(TG3_CPMU_EEE_CTRL,
4768 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4770 tw32_f(TG3_CPMU_EEE_DBTMR1,
4774 tw32_f(TG3_CPMU_EEE_DBTMR2,
4791 tw32_f(MAC_MI_MODE,
5045 tw32_f(MAC_MI_MODE, tp->mi_mode);
5049 tw32_f(MAC_MODE, tp->mac_mode);
5056 tw32_f(MAC_EVENT, 0);
5058 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5067 tw32_f(MAC_STATUS,
5237 tw32_f(MAC_MODE, tp->mac_mode);
5266 tw32_f(MAC_MODE, tp->mac_mode);
5281 tw32_f(MAC_MODE, tp->mac_mode);
5367 tw32_f(MAC_MODE, tp->mac_mode);
5416 tw32_f(MAC_TX_AUTO_NEG, 0);
5419 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5422 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5439 tw32_f(MAC_MODE, tp->mac_mode);
5539 tw32_f(MAC_SERDES_CFG, val);
5542 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5572 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5573 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5575 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5617 tw32_f(MAC_SERDES_CFG, val);
5620 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5681 tw32_f(MAC_STATUS,
5702 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5705 tw32_f(MAC_MODE, tp->mac_mode);
5736 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5742 tw32_f(MAC_TX_AUTO_NEG, 0);
5746 tw32_f(MAC_MODE, tp->mac_mode);
5753 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5770 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5784 tw32_f(MAC_MODE, (tp->mac_mode |
5787 tw32_f(MAC_MODE, tp->mac_mode);
5856 tw32_f(MAC_MODE, tp->mac_mode);
5865 tw32_f(MAC_MODE, tp->mac_mode);
5906 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5998 tw32_f(MAC_MODE, tp->mac_mode);
6001 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
6157 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
7037 tw32_f(MAC_STATUS,
7219 tw32_f(HOSTCC_MODE, tp->coal_now);
8269 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8271 tw32_f(MAC_RX_MODE, tp->rx_mode);
8859 tw32_f(ofs, val);
8901 tw32_f(MAC_RX_MODE, tp->rx_mode);
8920 tw32_f(MAC_MODE, tp->mac_mode);
8924 tw32_f(MAC_TX_MODE, tp->tx_mode);
9291 tw32_f(MAC_MODE, val);
9821 tw32_f(MAC_RX_MODE, rx_mode);
10020 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
10439 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10452 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10483 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10497 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10526 tw32_f(WDMAC_MODE, val);
10545 tw32_f(RDMAC_MODE, rdmac_mode);
10621 tw32_f(MAC_TX_MODE, tp->tx_mode);
10650 tw32_f(MAC_RX_MODE, tp->rx_mode);
10657 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10660 tw32_f(MAC_RX_MODE, tp->rx_mode);
10684 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
11076 tw32_f(MAC_MODE,
11080 tw32_f(MAC_MODE, tp->mac_mode);
11327 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13566 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13593 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
15045 tw32_f(GRC_EEPROM_ADDR,
15053 tw32_f(GRC_LOCAL_CTRL,
17048 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
17282 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17287 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);