Lines Matching defs:tw32
619 #define tw32(reg, val) tp->write32(tp, reg, val)
1000 tw32(TG3PCI_MISC_HOST_CTRL,
1013 tw32(TG3PCI_MISC_HOST_CTRL,
1030 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1032 tw32(HOSTCC_MODE, tp->coal_now);
1077 tw32(HOSTCC_MODE, tp->coalesce_mode |
1436 tw32(MAC_PHYCFG2, val);
1442 tw32(MAC_PHYCFG1, val);
1455 tw32(MAC_PHYCFG2, val);
1468 tw32(MAC_PHYCFG1, val);
1489 tw32(MAC_EXT_RGMII_MODE, val);
2055 tw32(MAC_MI_STAT,
2059 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2063 tw32(MAC_TX_LENGTHS,
2068 tw32(MAC_TX_LENGTHS,
2408 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2423 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2443 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2668 tw32(TG3_CPMU_CTRL,
2680 tw32(TG3_CPMU_CTRL, cpmuctrl);
2809 tw32(TG3_CPMU_DRV_STATUS, status);
3075 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3076 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3142 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3149 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3175 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3185 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3201 tw32(GRC_EEPROM_ADDR,
3235 tw32(NVRAM_CMD, nvram_cmd);
3304 tw32(NVRAM_ADDR, offset);
3348 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3351 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3355 tw32(GRC_EEPROM_ADDR, val |
3429 tw32(NVRAM_ADDR, phy_addr);
3448 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3450 tw32(NVRAM_ADDR, phy_addr + j);
3487 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3506 tw32(NVRAM_ADDR, phy_addr);
3553 tw32(NVRAM_WRITE1, 0x406);
3556 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3567 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3593 tw32(cpu_base + CPU_STATE, 0xffffffff);
3594 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3609 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3625 tw32(cpu_base + CPU_STATE, 0xffffffff);
3645 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3669 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3734 tw32(cpu_base + CPU_STATE, 0xffffffff);
3735 tw32(cpu_base + CPU_MODE,
3772 tw32(cpu_base + CPU_STATE, 0xffffffff);
3778 tw32(cpu_base + CPU_STATE, 0xffffffff);
3779 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3961 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3962 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3965 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3966 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3995 tw32(MAC_TX_BACKOFF_SEED, addr_high);
4040 tw32(TG3PCI_MISC_HOST_CTRL,
4113 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4170 tw32(MAC_LED_CTRL, tp->led_ctrl);
4256 tw32(0x7d00, val);
4355 tw32(TG3_CPMU_EEE_MODE,
4733 tw32(MAC_EVENT, 0);
5023 tw32(MAC_LED_CTRL, led_ctrl);
5235 tw32(MAC_TX_AUTO_NEG, 0);
5264 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5279 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5794 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5800 tw32(MAC_LED_CTRL, (tp->led_ctrl |
6095 tw32(GRC_MISC_CFG, val);
6108 tw32(MAC_TX_LENGTHS, val |
6111 tw32(MAC_TX_LENGTHS, val |
6116 tw32(HOSTCC_STAT_COAL_TICKS,
6119 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6130 tw32(PCIE_PWR_MGMT_THRESH, val);
6154 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6155 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6156 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6215 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6219 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6309 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6310 tw32(TG3_EAV_WATCHDOG0_MSB,
6314 tw32(TG3_EAV_REF_CLCK_CTL,
6317 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6318 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
7280 tw32(HOSTCC_MODE, tp->coalesce_mode |
8202 tw32(MAC_MODE, tp->mac_mode);
8293 tw32(MAC_MODE, mac_mode);
8942 tw32(FTQ_RESET, 0xffffffff);
8943 tw32(FTQ_RESET, 0x00000000);
9020 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
9032 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9038 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9053 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9060 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9097 tw32(GRC_FASTBOOT_PC, 0);
9136 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9148 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9151 tw32(GRC_MISC_CFG, (1 << 29));
9157 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9158 tw32(GRC_VCPU_EXT_CTRL,
9173 tw32(GRC_MISC_CFG, val);
9245 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9249 tw32(0x5000, 0x400);
9266 tw32(GRC_MODE, tp->grc_mode);
9271 tw32(0xc4, val | (1 << 15));
9279 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9304 tw32(0x7c00, val | (1 << 25));
9314 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9449 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9450 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9451 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9453 tw32(HOSTCC_TXCOL_TICKS, 0);
9454 tw32(HOSTCC_TXMAX_FRAMES, 0);
9455 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9461 tw32(reg, ec->tx_coalesce_usecs);
9463 tw32(reg, ec->tx_max_coalesced_frames);
9465 tw32(reg, ec->tx_max_coalesced_frames_irq);
9470 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9471 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9472 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9482 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9483 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9484 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9487 tw32(HOSTCC_RXCOL_TICKS, 0);
9488 tw32(HOSTCC_RXMAX_FRAMES, 0);
9489 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9496 tw32(reg, ec->rx_coalesce_usecs);
9498 tw32(reg, ec->rx_max_coalesced_frames);
9500 tw32(reg, ec->rx_max_coalesced_frames_irq);
9504 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9505 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9506 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9518 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9519 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9524 tw32(HOSTCC_STAT_COAL_TICKS, val);
9665 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9667 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9674 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9675 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9706 tw32(RCVBDI_STD_THRESH, val);
9709 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9719 tw32(RCVBDI_JUMBO_THRESH, val);
9722 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9752 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9753 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9754 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9755 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9799 tw32(MAC_HASH_REG_0, mc_filter[0]);
9800 tw32(MAC_HASH_REG_1, mc_filter[1]);
9801 tw32(MAC_HASH_REG_2, mc_filter[2]);
9802 tw32(MAC_HASH_REG_3, mc_filter[3]);
9868 tw32(reg, val);
9920 tw32(TG3_CPMU_CTRL, val);
9925 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9930 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9935 tw32(TG3_CPMU_HST_ACC, val);
9942 tw32(PCIE_PWR_MGMT_THRESH, val);
9945 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9947 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9950 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9958 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9961 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9964 tw32(GRC_MODE, grc_mode);
9973 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9977 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9980 tw32(GRC_MODE, grc_mode);
9989 tw32(TG3_CPMU_PADRNG_CTL, val);
9995 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
10000 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
10003 tw32(GRC_MODE, grc_mode);
10009 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
10027 tw32(TG3PCI_PCISTATE, val);
10038 tw32(TG3PCI_PCISTATE, val);
10045 tw32(TG3PCI_MSI_DATA, val);
10066 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10072 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10091 tw32(TG3_RX_PTP_CTL,
10097 tw32(GRC_MODE, tp->grc_mode | val);
10106 tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);
10113 tw32(GRC_MISC_CFG, val);
10119 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10121 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10123 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10124 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10125 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10131 tw32(BUFMGR_MB_POOL_ADDR,
10133 tw32(BUFMGR_MB_POOL_SIZE,
10138 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10140 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10142 tw32(BUFMGR_MB_HIGH_WATER,
10145 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10147 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10149 tw32(BUFMGR_MB_HIGH_WATER,
10152 tw32(BUFMGR_DMA_LOW_WATER,
10154 tw32(BUFMGR_DMA_HIGH_WATER,
10165 tw32(BUFMGR_MODE, val);
10177 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10198 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10200 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10203 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10208 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10218 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10220 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10224 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10229 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10232 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10245 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10260 tw32(MAC_RX_MTU_SIZE,
10276 tw32(MAC_TX_LENGTHS, val);
10279 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10280 tw32(RCVLPC_CONFIG, 0x0181);
10359 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10373 tw32(tgtreg, val |
10382 tw32(RCVLPC_STATS_ENABLE, val);
10387 tw32(RCVLPC_STATS_ENABLE, val);
10389 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10391 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10392 tw32(SNDDATAI_STATSENAB, 0xffffff);
10393 tw32(SNDDATAI_STATSCTRL,
10398 tw32(HOSTCC_MODE, 0);
10412 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10414 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10416 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10418 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10429 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10431 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10432 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10434 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10493 tw32(MSGINT_MODE, val);
10557 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10562 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10564 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10567 tw32(SNDDATAC_MODE,
10570 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10572 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10573 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10577 tw32(RCVDBDI_MODE, val);
10578 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10582 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10586 tw32(SNDBDI_MODE, val);
10587 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10632 tw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]);
10653 tw32(MAC_LED_CTRL, tp->led_ctrl);
10655 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10671 tw32(MAC_SERDES_CFG, val);
10674 tw32(MAC_SERDES_CFG, 0x616000);
10697 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10700 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10727 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10728 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10729 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10730 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10740 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10743 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10746 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10749 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10752 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10755 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10758 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10761 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10764 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10767 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10770 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10773 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10776 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10778 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10810 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10936 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10965 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
11024 tw32(GRC_LOCAL_CTRL,
11027 tw32(HOSTCC_MODE, tp->coalesce_mode |
11316 tw32(MSGINT_MODE, val);
11362 tw32(MSGINT_MODE, val);
11560 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11656 tw32(PCIE_TRANSACTION_CFG,
12060 tw32(TG3_CPMU_CTRL, cpmu_val &
12124 tw32(TG3_CPMU_CTRL, cpmu_val);
12807 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12817 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12822 tw32(MAC_LED_CTRL, tp->led_ctrl);
13315 tw32(offset, 0);
13327 tw32(offset, read_mask | write_mask);
13339 tw32(offset, save_val);
13348 tw32(offset, save_val);
13498 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13715 tw32(i, 0x0);
13959 tw32(TG3_RX_PTP_CTL,
14433 tw32(NVRAM_CFG1, nvcfg1);
14539 tw32(NVRAM_CFG1, nvcfg1);
14615 tw32(NVRAM_CFG1, nvcfg1);
14733 tw32(NVRAM_CFG1, nvcfg1);
14806 tw32(NVRAM_CFG1, nvcfg1);
14923 tw32(NVRAM_CFG1, nvcfg1);
15447 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15448 tw32(OTP_CTRL, cmd);
15469 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15474 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15481 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
16679 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16876 tw32(GRC_MODE, val | tp->grc_mode);
16881 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16884 tw32(TG3PCI_REG_BASE_ADDR, 0);
17254 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17255 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17256 tw32(RDMAC_STATUS, 0);
17257 tw32(WDMAC_STATUS, 0);
17259 tw32(BUFMGR_MODE, 0);
17260 tw32(FTQ_RESET, 0);
17303 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17305 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17421 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17433 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17467 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17498 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17953 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);