Lines Matching defs:tr32
622 #define tr32(reg) tp->read32(tp, reg)
668 *val = tr32(TG3PCI_MEM_WIN_DATA);
1089 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1144 frame_val = tr32(MAC_MI_COM);
1148 frame_val = tr32(MAC_MI_COM);
1206 frame_val = tr32(MAC_MI_COM);
1209 frame_val = tr32(MAC_MI_COM);
1438 val = tr32(MAC_PHYCFG1);
1457 val = tr32(MAC_PHYCFG1);
1470 val = tr32(MAC_EXT_RGMII_MODE);
1515 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1517 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1624 val = tr32(GRC_RX_CPU_EVENT);
1654 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1828 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
2380 val = tr32(TG3_CPMU_EEE_MODE);
2384 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2422 val = tr32(TG3_CPMU_EEE_MODE);
2442 val = tr32(TG3_CPMU_EEE_MODE);
2640 val = tr32(GRC_MISC_CFG);
2666 cpmuctrl = tr32(TG3_CPMU_CTRL);
2685 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2799 status = tr32(TG3_CPMU_DRV_STATUS);
3070 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3071 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3083 val = tr32(GRC_MISC_CFG);
3126 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3144 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3173 u32 nvaccess = tr32(NVRAM_ACCESS);
3183 u32 nvaccess = tr32(NVRAM_ACCESS);
3198 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3209 tmp = tr32(GRC_EEPROM_ADDR);
3218 tmp = tr32(GRC_EEPROM_DATA);
3238 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3309 *val = tr32(NVRAM_RDDATA);
3350 val = tr32(GRC_EEPROM_ADDR);
3362 val = tr32(GRC_EEPROM_ADDR);
3555 grc_mode = tr32(GRC_MODE);
3566 grc_mode = tr32(GRC_MODE);
3595 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3643 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3736 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3776 if (tr32(cpu_base + CPU_PC) == pc)
3819 tr32(RX_CPU_BASE + CPU_PC),
3839 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3942 __func__, tr32(cpu_base + CPU_PC),
4039 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4112 val = tr32(GRC_VCPU_EXT_CTRL);
4253 u32 val = tr32(0x7d00);
4356 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
5011 u32 led_ctrl = tr32(MAC_LED_CTRL);
5176 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5177 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5455 u32 mac_status = tr32(MAC_STATUS);
5520 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5525 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5528 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5581 sg_dig_status = tr32(SG_DIG_STATUS);
5582 mac_status = tr32(MAC_STATUS);
5626 mac_status = tr32(MAC_STATUS);
5685 if ((tr32(MAC_STATUS) &
5691 mac_status = tr32(MAC_STATUS);
5729 mac_status = tr32(MAC_STATUS);
5758 mac_status = tr32(MAC_STATUS);
5773 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5779 mac_status = tr32(MAC_STATUS);
5878 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5947 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
6085 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6093 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6102 val |= tr32(MAC_TX_LENGTHS) &
6124 val = tr32(PCIE_PWR_MGMT_THRESH);
6142 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6144 stamp |= (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6152 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6286 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6399 *dst++ = tr32(off + i);
6472 regs[i / sizeof(u32)] = tr32(i);
6574 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6575 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6887 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6888 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
7307 val = tr32(HOSTCC_FLOW_ATTN);
7313 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7318 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7535 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7584 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7630 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
8857 val = tr32(ofs);
8871 val = tr32(ofs);
8928 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8934 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
9019 val = tr32(MSGINT_MODE);
9031 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9052 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9059 val = tr32(TG3_CPMU_CLCK_ORIDE);
9135 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9146 tr32(TG3_PCIE_PHY_TSTCTL) ==
9157 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9159 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9244 val = tr32(MEMARB_MODE);
9269 val = tr32(0xc4);
9302 val = tr32(0x7c00);
9313 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9404 addr0_high = tr32(MAC_ADDR_0_HIGH);
9405 addr0_low = tr32(MAC_ADDR_0_LOW);
9406 addr1_high = tr32(MAC_ADDR_1_HIGH);
9407 addr1_low = tr32(MAC_ADDR_1_LOW);
9918 val = tr32(TG3_CPMU_CTRL);
9922 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9927 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9932 val = tr32(TG3_CPMU_HST_ACC);
9939 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9944 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9949 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9954 u32 grc_mode = tr32(GRC_MODE);
9960 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9969 u32 grc_mode = tr32(GRC_MODE);
9975 val = tr32(TG3_PCIE_TLDLPL_PORT +
9987 val = tr32(TG3_CPMU_PADRNG_CTL);
9991 grc_mode = tr32(GRC_MODE);
9997 val = tr32(TG3_PCIE_TLDLPL_PORT +
10006 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
10025 val = tr32(TG3PCI_PCISTATE);
10034 val = tr32(TG3PCI_PCISTATE);
10043 val = tr32(TG3PCI_MSI_DATA);
10058 val = tr32(TG3PCI_DMA_RW_CTRL) &
10105 val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;
10110 val = tr32(GRC_MISC_CFG);
10167 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10177 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10272 val |= tr32(MAC_TX_LENGTHS) &
10306 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10335 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10349 val = tr32(tgtreg);
10372 val = tr32(tgtreg);
10380 val = tr32(RCVLPC_STATS_ENABLE);
10385 val = tr32(RCVLPC_STATS_ENABLE);
10400 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10476 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10487 val = tr32(MSGINT_MODE);
10513 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10551 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10555 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10618 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10668 val = tr32(MAC_SERDES_CFG);
10696 tmp = tr32(SERDES_RX_CTRL);
10903 do { u32 __val = tr32(REG); \
10934 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10962 u32 val = tr32(HOSTCC_FLOW_ATTN);
11015 tr32(HOSTCC_MODE);
11031 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11050 mac_stat = tr32(MAC_STATUS);
11062 u32 mac_stat = tr32(MAC_STATUS);
11089 u32 cpmu = tr32(TG3_CPMU_STATUS);
11315 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11334 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11361 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11555 u32 msi_mode = tr32(MSGINT_MODE);
11654 u32 val = tr32(PCIE_TRANSACTION_CFG);
12057 cpmu_val = tr32(TG3_CPMU_CTRL);
13307 save_val = tr32(offset);
13317 val = tr32(offset);
13329 val = tr32(offset);
13745 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
14428 nvcfg1 = tr32(NVRAM_CFG1);
14506 nvcfg1 = tr32(NVRAM_CFG1);
14547 nvcfg1 = tr32(NVRAM_CFG1);
14603 nvcfg1 = tr32(NVRAM_CFG1);
14641 nvcfg1 = tr32(NVRAM_CFG1);
14681 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14723 nvcfg1 = tr32(NVRAM_CFG1);
14796 nvcfg1 = tr32(NVRAM_CFG1);
14874 nvcfg1 = tr32(NVRAM_CFG1);
14894 nv_status = tr32(NVRAM_AUTOSENSE_STATUS);
15054 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
15204 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
15208 val = tr32(VCPU_CFGSHDW);
15452 val = tr32(OTP_STATUS);
15479 thalf_otp = tr32(OTP_READ_DATA);
15486 bhalf_otp = tr32(OTP_READ_DATA);
16226 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16678 val = tr32(MEMARB_MODE);
16695 val = tr32(TG3_CPMU_STATUS);
16773 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16865 val = tr32(GRC_MODE);
16918 grc_misc_cfg = tr32(GRC_MISC_CFG);
17020 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
17045 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
17084 hi = tr32(MAC_ADDR_0_HIGH);
17085 lo = tr32(MAC_ADDR_0_LOW);
17312 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17314 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17366 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17601 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17606 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17889 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17950 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17951 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {