Lines Matching defs:tg3_writephy
1229 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1238 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1242 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1246 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1251 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1261 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1265 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1269 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1284 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1295 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1297 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1306 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1320 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1346 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1359 err = tg3_writephy(tp, MII_BMCR, phy_control);
2211 tg3_writephy(tp, MII_TG3_FET_TEST,
2218 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2220 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2269 tg3_writephy(tp, MII_TG3_FET_TEST,
2276 tg3_writephy(tp, reg, phy);
2278 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2477 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2479 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2482 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2485 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2491 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2499 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2518 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2519 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2520 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2537 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2539 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2541 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2542 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2570 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2573 tg3_writephy(tp, MII_BMCR,
2580 tg3_writephy(tp, MII_CTRL1000,
2601 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2602 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2606 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2613 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2714 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2715 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2727 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2729 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2730 tg3_writephy(tp, MII_TG3_TEST1,
2733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2758 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2764 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
3092 tg3_writephy(tp, MII_ADVERTISE, 0);
3093 tg3_writephy(tp, MII_BMCR,
3096 tg3_writephy(tp, MII_TG3_FET_TEST,
3100 tg3_writephy(tp,
3104 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3109 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3132 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
4336 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4347 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4452 tg3_writephy(tp, MII_BMCR,
4466 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4489 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4502 tg3_writephy(tp, MII_BMCR, bmcr);
4848 tg3_writephy(tp, 0x15, 0x0a75);
4849 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4850 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4851 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4859 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4861 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4866 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4869 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
5464 tg3_writephy(tp, 0x16, 0x8007);
5467 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5475 tg3_writephy(tp, 0x10, 0x8411);
5478 tg3_writephy(tp, 0x11, 0x0a10);
5480 tg3_writephy(tp, 0x18, 0x00a0);
5481 tg3_writephy(tp, 0x16, 0x41ff);
5484 tg3_writephy(tp, 0x13, 0x0400);
5486 tg3_writephy(tp, 0x13, 0x0000);
5488 tg3_writephy(tp, 0x11, 0x0a50);
5490 tg3_writephy(tp, 0x11, 0x0a10);
5500 tg3_writephy(tp, 0x10, 0x8011);
5902 tg3_writephy(tp, MII_ADVERTISE, newadv);
5904 tg3_writephy(tp, MII_BMCR, bmcr);
5935 tg3_writephy(tp, MII_ADVERTISE, adv);
5936 tg3_writephy(tp, MII_BMCR, bmcr |
5942 tg3_writephy(tp, MII_BMCR, new_bmcr);
6027 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6031 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6044 tg3_writephy(tp, MII_BMCR, bmcr);
6054 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6062 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
8239 tg3_writephy(tp, MII_CTRL1000, val);
8243 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8248 tg3_writephy(tp, MII_BMCR, bmcr);
8258 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8289 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10717 tg3_writephy(tp, MII_TG3_TEST1,
11830 tg3_writephy(tp, MII_TG3_TEST1,
12438 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
15658 tg3_writephy(tp, MII_BMCR,