Lines Matching defs:set
1315 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1318 set |= MII_TG3_AUXCTL_MISC_WREN;
1320 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
3687 * the main header, the length field is unused and set to 0xffffffff.
3817 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3880 * here is unused and set to 0xffffffff.
3941 "%s fails to set CPU PC, is %08x should be %08x\n",
5008 * in RGMII mode, the Led Control Register must be set up.
5923 * to be set on write.
7190 /* run RX thread, within the bounds set by NAPI.
8415 /* Initialize invariants of the rings, we only set this
8698 * set on vector zero. This is the true hw prodring.
8755 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set.
10014 * other revision. But do not set this on PCI Express
10455 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10458 * whether used as inputs or outputs, are set by boot code after
10667 /* only if the signal pre-emphasis bit is not set */
14535 /* For eeprom, set pagesize to maximum eeprom size */
15366 /* serdes signal pre-emphasis in register 0x590 set by */
15367 /* bootcode if bit 18 is set */
15586 /* Do nothing, phy ID already set up in
16118 /* 5704 can be configured in single-port mode, set peer to
16255 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16713 * When the flag is set, it means that GPIO1 is used for eeprom
16975 /* The led_ctrl is set during tg3_phy_probe, here we might
17408 /* On 5700/5701 chips, we need to set this bit.
18272 * set up identically to what it was at cold boot.