Lines Matching defs:offset
3190 u32 offset, u32 *val)
3195 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3204 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3286 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3291 return tg3_nvram_read_using_eeprom(tp, offset, val);
3293 offset = tg3_nvram_phys_addr(tp, offset);
3295 if (offset > NVRAM_ADDR_MSK)
3304 tw32(NVRAM_ADDR, offset);
3319 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3322 int res = tg3_nvram_read(tp, offset, &v);
3329 u32 offset, u32 len, u8 *buf)
3338 addr = offset + i;
3377 /* offset and length are dword aligned */
3378 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3395 phy_addr = offset & ~pagemask;
3406 page_off = offset & pagemask;
3415 offset = offset + (pagesize - page_off);
3476 /* offset and length are dword aligned */
3477 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3482 for (i = 0; i < len; i += 4, offset += 4) {
3489 page_off = offset % tp->nvram_pagesize;
3491 phy_addr = tg3_nvram_phys_addr(tp, offset);
3531 /* offset and length are dword aligned */
3532 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3543 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3559 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3562 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12043 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
12049 offset = eeprom->offset;
12068 if (offset & 3) {
12070 b_offset = offset & 3;
12073 /* i.e. offset=1 len=2 */
12076 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
12081 offset += b_count;
12088 ret = tg3_nvram_read_be32(tp, offset + i, &val);
12111 b_offset = offset + len - b_count;
12133 u32 offset, len, b_offset, odd_len;
12141 offset = eeprom->offset;
12144 if ((b_offset = (offset & 3))) {
12146 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12150 offset &= ~3;
12160 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12177 ret = tg3_nvram_write_block(tp, offset, len, buf);
12844 u32 offset = 0, len = 0;
12851 for (offset = TG3_NVM_DIR_START;
12852 offset < TG3_NVM_DIR_END;
12853 offset += TG3_NVM_DIRENT_SIZE) {
12854 if (tg3_nvram_read(tp, offset, &val))
12862 if (offset != TG3_NVM_DIR_END) {
12864 if (tg3_nvram_read(tp, offset + 4, &offset))
12867 offset = tg3_nvram_logical_addr(tp, offset);
12871 if (!offset || !len) {
12872 offset = TG3_NVM_VPD_OFF;
12886 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
13057 /* Bootstrap checksum at offset 0x10 */
13062 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
13135 u32 offset, read_mask, write_mask, val, save_val, read_val;
13137 u16 offset;
13288 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13302 offset = (u32) reg_tbl[i].offset;
13307 save_val = tr32(offset);
13315 tw32(offset, 0);
13317 val = tr32(offset);
13327 tw32(offset, read_mask | write_mask);
13329 val = tr32(offset);
13339 tw32(offset, save_val);
13347 "Register test failed at offset %x\n", offset);
13348 tw32(offset, save_val);
13352 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13362 tg3_write_mem(tp, offset + j, test_pattern[i]);
13363 tg3_read_mem(tp, offset + j, &val);
13374 u32 offset;
13432 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13433 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
14407 * 16-bit value at offset 0xf2. The tg3_nvram_read()
15409 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15412 u32 val2, off = offset * 8;
15799 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15803 if (tg3_nvram_read(tp, offset, &val) ||
15805 tg3_nvram_read(tp, offset + 4, &val) ||
15814 u32 val, offset, start, ver_offset;
15818 if (tg3_nvram_read(tp, 0xc, &offset) ||
15822 offset = tg3_nvram_logical_addr(tp, offset);
15824 if (tg3_nvram_read(tp, offset, &val))
15828 if (tg3_nvram_read(tp, offset + 4, &val))
15839 tg3_nvram_read(tp, offset + 8, &ver_offset))
15842 offset = offset + ver_offset - start;
15845 if (tg3_nvram_read_be32(tp, offset + i, &v))
15882 u32 offset, major, minor, build;
15891 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15894 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15897 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15900 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15903 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15906 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15912 if (tg3_nvram_read(tp, offset, &val))
15924 offset = strlen(tp->fw_ver);
15925 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15929 offset = strlen(tp->fw_ver);
15930 if (offset < TG3_VER_SIZE - 1)
15931 tp->fw_ver[offset] = 'a' + build - 1;
15937 u32 val, offset, start;
15940 for (offset = TG3_NVM_DIR_START;
15941 offset < TG3_NVM_DIR_END;
15942 offset += TG3_NVM_DIRENT_SIZE) {
15943 if (tg3_nvram_read(tp, offset, &val))
15950 if (offset == TG3_NVM_DIR_END)
15955 else if (tg3_nvram_read(tp, offset - 4, &start))
15958 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15959 !tg3_fw_img_is_valid(tp, offset) ||
15960 tg3_nvram_read(tp, offset + 8, &val))
15963 offset += val - start;
15972 if (tg3_nvram_read_be32(tp, offset, &v))
15975 offset += sizeof(v);