Lines Matching defs:off
469 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
471 writel(val, tp->regs + off);
474 static u32 tg3_read32(struct tg3 *tp, u32 off)
476 return readl(tp->regs + off);
479 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
481 writel(val, tp->aperegs + off);
484 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
486 return readl(tp->aperegs + off);
489 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
494 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
499 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
501 writel(val, tp->regs + off);
502 readl(tp->regs + off);
505 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
511 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
517 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
521 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
526 if (off == TG3_RX_STD_PROD_IDX_REG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
540 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
547 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
553 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
564 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
568 tp->write32(tp, off, val);
571 tg3_write32(tp, off, val);
574 tp->read32(tp, off);
583 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
585 tp->write32_mbox(tp, off, val);
589 tp->read32_mbox(tp, off);
592 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
594 void __iomem *mbox = tp->regs + off;
603 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
605 return readl(tp->regs + off + GRCMBOX_BASE);
608 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
610 writel(val, tp->regs + off + GRCMBOX_BASE);
624 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
629 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
634 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
640 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
649 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
654 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
661 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
667 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
708 int i, off;
745 off = 4 * locknum;
747 tg3_ape_write32(tp, req + off, bit);
751 status = tg3_ape_read32(tp, gnt + off);
762 tg3_ape_write32(tp, gnt + off, bit);
1892 "on" : "off",
1894 "on" : "off");
4609 /* Turn off tap power management. */
6393 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6397 dst = (u32 *)((u8 *)dst + off);
6399 *dst++ = tr32(off + i);
10818 u32 off, len = TG3_OCIR_LEN;
10821 for (i = 0, off = 0; i < TG3_SD_NUM_RECS; i++, ocir++, off += len) {
10822 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
11311 * Turn off MSI one shot mode. Otherwise this test has no
11381 /* Turn off SERR reporting in case MSI terminates with Master
12804 return 1; /* cycle on/off once per second */
15412 u32 val2, off = offset * 8;
15418 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
16253 /* Force memory write invalidate off. If we leave it on,
16257 * workaround but turns MWI off all the times so never uses
16763 /* Turn off the debug UART. */
17847 * is off by default, but can be enabled using ethtool.