Lines Matching defs:err
847 int err;
878 err = tg3_ape_event_lock(tp, 1000);
879 if (err)
880 return err;
911 int err;
923 err = tg3_ape_event_lock(tp, 20000);
924 if (err)
925 return err;
1236 int err;
1238 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1239 if (err)
1242 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1243 if (err)
1246 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1248 if (err)
1251 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1254 return err;
1259 int err;
1261 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1262 if (err)
1265 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1266 if (err)
1269 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1271 if (err)
1274 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1277 return err;
1282 int err;
1284 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1285 if (!err)
1286 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1288 return err;
1293 int err;
1295 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1296 if (!err)
1297 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1299 return err;
1304 int err;
1306 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1309 if (!err)
1310 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1312 return err;
1326 int err;
1328 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1330 if (err)
1331 return err;
1338 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1341 return err;
1353 int limit, err;
1359 err = tg3_writephy(tp, MII_BMCR, phy_control);
1360 if (err != 0)
1365 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1366 if (err != 0)
2176 int err;
2184 err = tg3_phy_auxctl_write(tp,
2191 err = tg3_phy_auxctl_read(tp,
2193 if (err)
2194 return err;
2197 err = tg3_phy_auxctl_write(tp,
2201 return err;
2553 int retries, do_phy_reset, err;
2559 err = tg3_bmcr_reset(tp);
2560 if (err)
2561 return err;
2583 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2584 if (err)
2585 return err;
2590 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2591 if (!err)
2595 err = tg3_phy_reset_chanpat(tp);
2596 if (err)
2597 return err;
2608 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2609 if (err)
2610 return err;
2637 int err;
2644 err = tg3_readphy(tp, MII_BMSR, &val);
2645 err |= tg3_readphy(tp, MII_BMSR, &val);
2646 if (err != 0)
2657 err = tg3_phy_reset_5703_4_5(tp);
2658 if (err)
2659 return err;
2672 err = tg3_bmcr_reset(tp);
2673 if (err)
2674 return err;
2746 err = tg3_phy_auxctl_read(tp,
2748 if (!err)
3705 int err, i;
3726 err = tg3_halt_cpu(tp, cpu_base);
3729 if (err)
3760 err = 0;
3763 return err;
3791 int err;
3801 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3804 if (err)
3805 return err;
3807 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3810 if (err)
3811 return err;
3814 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3816 if (err) {
3906 int err;
3930 err = tg3_load_firmware_cpu(tp, cpu_base,
3933 if (err)
3934 return err;
3937 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3939 if (err) {
4010 int err;
4014 err = pci_set_power_state(tp->pdev, PCI_D0);
4015 if (!err) {
4022 return err;
4258 int err;
4260 err = tg3_nvram_lock(tp);
4262 if (!err)
4329 int err = 0;
4336 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4337 if (err)
4347 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4348 if (err)
4358 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4359 if (!err) {
4379 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4380 if (err)
4403 if (!err)
4404 err = err2;
4408 return err;
4510 int err;
4513 err = tg3_readphy(tp, MII_BMCR, &val);
4514 if (err)
4522 err = -EIO;
4554 err = 0;
4565 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4566 if (err)
4581 err = tg3_readphy(tp, MII_CTRL1000, &val);
4582 if (err)
4587 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4588 if (err)
4602 return err;
4607 int err;
4611 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4613 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4614 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4615 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4616 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4617 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4621 return err;
4786 int i, err;
4820 err = tg3_init_5401phy_dsp(tp);
4821 if (err)
4822 return err;
4838 err = tg3_phy_reset(tp);
4839 if (!err)
4840 err = tg3_init_5401phy_dsp(tp);
4841 if (err)
4842 return err;
4879 err = tg3_phy_auxctl_read(tp,
4882 if (!err && !(val & (1 << 10))) {
5818 int err = 0;
5875 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5876 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5884 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5892 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5910 return err;
5931 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5944 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5945 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5970 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5971 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
6007 return err;
6073 int err;
6076 err = tg3_setup_fiber_phy(tp, force_reset);
6078 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6080 err = tg3_setup_copper_phy(tp, force_reset);
6133 return err;
7055 int i, err = 0;
7083 err = -ENOSPC;
7141 err = -ENOSPC;
7173 return err;
7199 int i, err = 0;
7205 err |= tg3_rx_prodring_xfer(tp, dpr,
7218 if (err)
8889 int i, err;
8896 err = -ENODEV;
8904 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8905 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8906 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8907 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8908 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8909 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8911 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8912 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8913 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8914 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8915 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8916 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8917 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8935 err |= -ENODEV;
8938 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8939 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8940 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8945 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8946 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8955 return err;
9075 int i, err;
9262 err = tg3_poll_fw(tp);
9263 if (err)
9264 return err;
9353 int err, i;
9360 err = tg3_chip_reset(tp);
9383 return err;
9390 int err = 0;
9419 return err;
9885 int i, err, limit;
9911 err = tg3_chip_reset(tp);
9912 if (err)
9913 return err;
10053 err = tg3_init_rings(tp);
10054 if (err)
10055 return err;
10590 err = tg3_load_5701_a0_firmware_fix(tp);
10591 if (err)
10592 return err;
10603 err = tg3_load_tso_firmware(tp);
10604 if (err)
10605 return err;
10707 err = tg3_setup_phy(tp, false);
10708 if (err)
10709 return err;
11181 int err;
11183 err = tg3_init_hw(tp, reset_phy);
11184 if (err) {
11195 return err;
11201 int err;
11230 err = tg3_init_hw(tp, true);
11231 if (err) {
11247 if (!err)
11300 int err, i, intr_ok = 0;
11319 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11321 if (err)
11322 return err;
11353 err = tg3_request_irq(tp, 0);
11355 if (err)
11356 return err;
11375 int err;
11388 err = tg3_test_interrupt(tp);
11392 if (!err)
11396 if (err != -EIO)
11397 return err;
11411 err = tg3_request_irq(tp, 0);
11412 if (err)
11413 return err;
11421 err = tg3_init_hw(tp, true);
11425 if (err)
11428 return err;
11592 int i, err;
11605 err = tg3_alloc_consistent(tp);
11606 if (err)
11614 err = tg3_request_irq(tp, i);
11615 if (err) {
11630 err = tg3_init_hw(tp, reset_phy);
11631 if (err) {
11638 if (err)
11642 err = tg3_test_msi(tp);
11644 if (err) {
11700 return err;
11741 int err;
11750 err = tg3_request_firmware(tp);
11752 if (err) {
11760 if (err)
11761 return err;
11762 } else if (err) {
11773 err = tg3_power_up(tp);
11774 if (err)
11775 return err;
11784 err = tg3_start(tp,
11787 if (err) {
11792 return err;
12472 int i, irq_sync = 0, err = 0;
12511 err = tg3_restart_hw(tp, reset_phy);
12512 if (!err)
12518 if (irq_sync && !err)
12521 return err;
12544 int err = 0;
12621 err = tg3_restart_hw(tp, reset_phy);
12622 if (!err)
12631 return err;
12930 int i, j, k, err = 0, size;
12976 err = -EIO;
12978 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12979 if (err)
13004 err = 0;
13008 err = -EIO;
13042 err = -EIO;
13051 err = 0;
13055 err = -EIO;
13098 err = 0;
13102 return err;
13415 int err = 0;
13433 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13434 if (err)
13438 return err;
13472 int num_pkts, tx_len, rx_len, i, err;
13487 err = -EIO;
13665 err = 0;
13669 return err;
13682 int err = -EIO;
13700 err = tg3_reset_hw(tp, true);
13701 if (err) {
13786 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13792 return err;
13821 int err, err2 = 0, irq_sync = 0;
13831 err = tg3_nvram_lock(tp);
13835 if (!err)
14036 int err;
14061 err = __tg3_readphy(tp, data->phy_id & 0x1f,
14067 return err;
14078 err = __tg3_writephy(tp, data->phy_id & 0x1f,
14082 return err;
14296 int err;
14326 err = tg3_restart_hw(tp, reset_phy);
14328 if (!err)
14333 if (!err)
14336 return err;
15411 int i, err;
15414 err = tg3_nvram_lock(tp);
15415 if (err)
15416 return err;
15524 int err;
15559 err = 0;
15568 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15569 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15578 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15648 err = tg3_phy_reset(tp);
15649 if (err)
15650 return err;
15665 err = tg3_init_5401phy_dsp(tp);
15666 if (err)
15667 return err;
15669 err = tg3_init_5401phy_dsp(tp);
15672 return err;
16251 int err;
16860 err = tg3_mdio_init(tp);
16861 if (err)
16862 return err;
16947 err = tg3_phy_probe(tp);
16948 if (err) {
16949 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
17023 return err;
17031 int err;
17037 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
17038 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
17445 "%s: Buffer write failed. err = %d\n",
17454 "err = %d\n", __func__, ret);
17667 int i, err;
17673 err = pci_enable_device(pdev);
17674 if (err) {
17676 return err;
17679 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17680 if (err) {
17689 err = -ENOMEM;
17750 err = -ENOMEM;
17774 err = -ENOMEM;
17787 err = tg3_get_invariants(tp, ent);
17788 if (err) {
17812 err = pci_set_dma_mask(pdev, dma_mask);
17813 if (!err) {
17815 err = pci_set_consistent_dma_mask(pdev,
17817 if (err < 0) {
17824 if (err || dma_mask == DMA_BIT_MASK(32)) {
17825 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17826 if (err) {
17894 err = tg3_get_device_address(tp);
17895 if (err) {
17958 err = tg3_test_dma(tp);
17959 if (err) {
17977 err = register_netdev(dev);
17978 if (err) {
18050 return err;
18091 int err = 0;
18115 err = tg3_power_down_prepare(tp);
18116 if (err) {
18140 return err;
18147 int err = 0;
18161 err = tg3_restart_hw(tp,
18163 if (err)
18173 if (!err)
18178 return err;
18219 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18255 err = PCI_ERS_RESULT_DISCONNECT;
18262 return err;
18279 int err;
18298 err = tg3_power_up(tp);
18299 if (err)
18325 int err;
18335 err = tg3_restart_hw(tp, true);
18336 if (err) {