Lines Matching refs:val
267 u32 val;
271 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);
273 return val;
277 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
283 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
288 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
290 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
300 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
309 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);
313 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);
314 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
320 BNX2_WR(bp, BNX2_CTX_DATA, val);
487 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
522 *val = 0x0;
526 *val = val1;
544 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
559 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
1051 u32 val;
1053 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1054 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1056 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1109 u32 val, speed;
1114 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1122 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1138 if (val & MII_BNX2_GP_TOP_AN_FD)
1148 u32 val;
1151 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1152 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1166 if (val & BCM5708S_1000X_STAT1_FD)
1290 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1292 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1293 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1294 val |= 0x02 << 8;
1297 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
1299 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1318 u32 val;
1327 val = BNX2_RD(bp, BNX2_EMAC_MODE);
1329 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1337 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1342 val |= BNX2_EMAC_MODE_PORT_MII;
1345 val |= BNX2_EMAC_MODE_25G_MODE;
1348 val |= BNX2_EMAC_MODE_PORT_GMII;
1353 val |= BNX2_EMAC_MODE_PORT_GMII;
1358 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1359 BNX2_WR(bp, BNX2_EMAC_MODE, val);
1369 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);
1370 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1373 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1374 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);
1465 u32 val;
1469 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1470 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1471 val |= MII_BNX2_SD_MISC1_FORCE |
1473 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1509 u32 val;
1513 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1514 val &= ~MII_BNX2_SD_MISC1_FORCE;
1515 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1541 u32 val;
1544 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1546 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1548 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1574 u32 val, an_dbg;
1580 val = BNX2_RD(bp, BNX2_EMAC_STATUS);
1586 if ((val & BNX2_EMAC_STATUS_LINK) &&
2183 u32 val;
2201 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2202 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2203 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2204 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2207 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2209 val |= BCM5708S_UP1_2G5;
2211 val &= ~BCM5708S_UP1_2G5;
2212 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2215 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2216 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2217 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2221 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2223 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2233 u32 val;
2244 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2245 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2246 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2248 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2249 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2250 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2253 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2254 val |= BCM5708S_UP1_2G5;
2255 bnx2_write_phy(bp, BCM5708S_UP1, val);
2264 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2265 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2266 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2270 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2273 if (val) {
2280 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2300 u32 val;
2304 bnx2_read_phy(bp, 0x18, &val);
2305 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2308 bnx2_read_phy(bp, 0x1c, &val);
2309 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2312 u32 val;
2315 bnx2_read_phy(bp, 0x18, &val);
2316 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2319 bnx2_read_phy(bp, 0x1c, &val);
2320 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2329 u32 val;
2348 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2349 val &= ~(1 << 8);
2350 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2356 bnx2_read_phy(bp, 0x18, &val);
2357 bnx2_write_phy(bp, 0x18, val | 0x4000);
2359 bnx2_read_phy(bp, 0x10, &val);
2360 bnx2_write_phy(bp, 0x10, val | 0x1);
2364 bnx2_read_phy(bp, 0x18, &val);
2365 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2367 bnx2_read_phy(bp, 0x10, &val);
2368 bnx2_write_phy(bp, 0x10, val & ~0x1);
2373 bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);
2374 val |= AUX_CTL_MISC_CTL_WR | AUX_CTL_MISC_CTL_WIRESPEED;
2378 val |= AUX_CTL_MISC_CTL_AUTOMDIX;
2380 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);
2390 u32 val;
2407 bnx2_read_phy(bp, MII_PHYSID1, &val);
2408 bp->phy_id = val << 16;
2409 bnx2_read_phy(bp, MII_PHYSID2, &val);
2410 bp->phy_id |= val & 0xffff;
2523 u32 val;
2538 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2540 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2547 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2560 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2570 u32 val;
2572 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2573 val |= (BNX2_PAGE_BITS - 8) << 16;
2574 BNX2_WR(bp, BNX2_CTX_COMMAND, val);
2576 val = BNX2_RD(bp, BNX2_CTX_COMMAND);
2577 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2581 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2601 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2602 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2606 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2662 u32 val;
2674 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2675 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2679 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2681 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2684 if (!(val & (1 << 9))) {
2685 good_mbuf[good_mbuf_cnt] = (u16) val;
2689 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2697 val = good_mbuf[good_mbuf_cnt];
2698 val = (val << 9) | val | 1;
2700 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2709 u32 val;
2711 val = (mac_addr[0] << 8) | mac_addr[1];
2713 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2715 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2718 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
3779 u32 val, cmd, addr;
3800 val = (i / 8) | cmd;
3801 BNX2_WR(bp, addr, val);
3816 val = (loc / 2) | cmd;
3817 BNX2_WR(bp, addr, val);
3839 u32 val;
3842 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3843 val |= cpu_reg->mode_value_halt;
3844 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3892 val = be32_to_cpu(fw_entry->start_addr);
3893 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3896 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3897 val &= ~cpu_reg->mode_value_halt;
3899 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3948 u32 val, wol_msg;
3975 val = BNX2_RD(bp, BNX2_EMAC_MODE);
3978 val &= ~BNX2_EMAC_MODE_PORT;
3979 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3983 val |= BNX2_EMAC_MODE_PORT_MII;
3985 val |= BNX2_EMAC_MODE_PORT_GMII;
3987 val |= BNX2_EMAC_MODE_25G_MODE;
3990 BNX2_WR(bp, BNX2_EMAC_MODE, val);
3999 val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN;
4001 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);
4002 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);
4010 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
4011 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
4012 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4020 u32 val;
4030 val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
4032 val | BNX2_PORT_FEATURE_ASF_ENABLED);
4034 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);
4044 u32 val;
4049 val = BNX2_RD(bp, BNX2_EMAC_MODE);
4050 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
4051 val &= ~BNX2_EMAC_MODE_MPKT;
4052 BNX2_WR(bp, BNX2_EMAC_MODE, val);
4054 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
4055 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
4056 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4071 u32 val;
4077 val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
4078 val &= ~BNX2_CONDITION_PM_STATE_MASK;
4079 val |= BNX2_CONDITION_PM_STATE_UNPREP;
4080 bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);
4098 u32 val;
4104 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4105 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4121 u32 val;
4127 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4128 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4144 u32 val;
4146 val = BNX2_RD(bp, BNX2_MISC_CFG);
4147 BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4159 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4160 if (val & BNX2_NVM_COMMAND_DONE)
4173 u32 val;
4175 val = BNX2_RD(bp, BNX2_MISC_CFG);
4176 BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4183 u32 val;
4185 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4188 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4194 u32 val;
4196 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4199 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4228 u32 val;
4232 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4233 if (val & BNX2_NVM_COMMAND_DONE)
4270 u32 val;
4274 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4275 if (val & BNX2_NVM_COMMAND_DONE) {
4289 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4308 memcpy(&val32, val, 4);
4335 u32 val;
4345 val = BNX2_RD(bp, BNX2_NVM_CFG1);
4349 if (val & 0x40000000) {
4354 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4365 if (val & (1 << 23))
4373 if ((val & mask) == (flash->strapping & mask)) {
4396 } /* if (val & 0x40000000) */
4405 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4406 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4407 if (val)
4408 bp->flash_size = val;
4708 u32 val, sig = 0;
4716 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4717 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4720 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4726 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4757 u32 val;
4771 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4774 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4775 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4776 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4777 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4781 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4782 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4794 u32 val;
4812 val = BNX2_RD(bp, BNX2_MISC_ID);
4819 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4822 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4825 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4830 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4842 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4843 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4849 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4857 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);
4858 if (val != 0x01020304) {
4898 u32 val, mtu;
4904 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4913 val |= (0x2 << 20) | (1 << 11);
4916 val |= (1 << 23);
4921 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4923 BNX2_WR(bp, BNX2_DMA_CONFIG, val);
4926 val = BNX2_RD(bp, BNX2_TDMA_CONFIG);
4927 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4928 BNX2_WR(bp, BNX2_TDMA_CONFIG, val);
4961 val = BNX2_RD(bp, BNX2_MQ_CONFIG);
4962 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4963 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4965 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4967 val |= BNX2_MQ_CONFIG_HALT_DIS;
4970 BNX2_WR(bp, BNX2_MQ_CONFIG, val);
4972 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4973 BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4974 BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4976 val = (BNX2_PAGE_BITS - 8) << 24;
4977 BNX2_WR(bp, BNX2_RV2P_CONFIG, val);
4980 val = BNX2_RD(bp, BNX2_TBDR_CONFIG);
4981 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4982 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40;
4983 BNX2_WR(bp, BNX2_TBDR_CONFIG, val);
4985 val = bp->mac_addr[0] +
4991 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4995 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4996 if (val > (MAX_ETHERNET_PACKET_SIZE + ETH_HLEN + 4))
4997 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4998 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
5051 val = BNX2_HC_CONFIG_COLLECT_STATS;
5053 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
5061 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
5065 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5067 BNX2_WR(bp, BNX2_HC_CONFIG, val);
5107 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5108 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5109 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5150 u32 val, offset0, offset1, offset2, offset3;
5164 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5165 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5167 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5168 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5170 val = (u64) txr->tx_desc_mapping >> 32;
5171 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5173 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5174 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5238 u32 cid, rx_cid_addr, val;
5255 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);
5256 BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5264 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5265 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5269 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5270 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5272 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5273 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5279 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5280 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5282 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5283 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5323 u32 val;
5358 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5361 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5687 u32 offset, rw_mask, ro_mask, save_val, val;
5701 val = readl(bp->regview + offset);
5702 if ((val & rw_mask) != 0) {
5706 if ((val & ro_mask) != (save_val & ro_mask)) {
5712 val = readl(bp->regview + offset);
5713 if ((val & rw_mask) != rw_mask) {
5717 if ((val & ro_mask) != (save_val & ro_mask)) {
6127 u32 val;
6130 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6131 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6133 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6139 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
7946 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7947 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7957 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7958 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7960 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;