Lines Matching refs:BNX2_WR
270 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
282 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
283 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
309 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);
310 BNX2_WR(bp, BNX2_CTX_CTX_CTRL,
319 BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);
320 BNX2_WR(bp, BNX2_CTX_DATA, val);
496 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
505 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
534 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
553 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
562 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
583 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
600 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
615 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
620 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
624 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
1320 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1323 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1359 BNX2_WR(bp, BNX2_EMAC_MODE, val);
1366 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1374 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);
1377 BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1968 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1969 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
2297 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2402 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2439 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
2471 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
2574 BNX2_WR(bp, BNX2_CTX_COMMAND, val);
2592 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2595 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2597 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2647 BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2648 BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2668 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2713 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2718 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2806 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2808 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
3300 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3316 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3364 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3432 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3434 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3473 BNX2_WR(bp, BNX2_HC_COMMAND,
3512 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3550 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3555 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3560 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3600 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3623 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3649 BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3652 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3653 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3654 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3795 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3797 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3801 BNX2_WR(bp, addr, val);
3811 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3814 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3817 BNX2_WR(bp, addr, val);
3823 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3826 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3990 BNX2_WR(bp, BNX2_EMAC_MODE, val);
3994 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3997 BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);
4000 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
4001 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);
4002 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);
4005 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4012 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4052 BNX2_WR(bp, BNX2_EMAC_MODE, val);
4056 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4102 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4124 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4147 BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4152 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4153 BNX2_WR(bp, BNX2_NVM_COMMAND,
4176 BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4187 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4198 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4218 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4221 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4224 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4260 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4263 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4266 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4306 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4311 BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4314 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4317 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4384 BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);
4385 BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);
4386 BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);
4387 BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4748 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4750 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4751 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4766 BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4776 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4815 BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4822 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4830 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4879 BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4888 BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,
4902 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4923 BNX2_WR(bp, BNX2_DMA_CONFIG, val);
4928 BNX2_WR(bp, BNX2_TDMA_CONFIG, val);
4940 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4970 BNX2_WR(bp, BNX2_MQ_CONFIG, val);
4973 BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4974 BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4977 BNX2_WR(bp, BNX2_RV2P_CONFIG, val);
4983 BNX2_WR(bp, BNX2_TBDR_CONFIG, val);
4991 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4998 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
5014 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
5016 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,
5018 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
5020 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
5022 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
5025 BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
5028 BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
5031 BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,
5034 BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
5036 BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
5038 BNX2_WR(bp, BNX2_HC_COM_TICKS,
5041 BNX2_WR(bp, BNX2_HC_CMD_TICKS,
5045 BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);
5047 BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
5048 BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
5058 BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
5067 BNX2_WR(bp, BNX2_HC_CONFIG, val);
5078 BNX2_WR(bp, base,
5083 BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
5087 BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
5090 BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5094 BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5099 BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5101 BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
5109 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5114 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5256 BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5276 BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5316 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5327 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5332 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5335 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5349 BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5350 BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
5361 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5852 BNX2_WR(bp, BNX2_HC_COMMAND,
5874 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5878 BNX2_WR(bp, BNX2_HC_COMMAND,
6033 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
6200 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6273 BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6274 BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6275 BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6529 BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);
6530 BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,
6532 BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);
6716 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
7716 BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7720 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7729 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7733 BNX2_WR(bp, BNX2_EMAC_LED, 0);
7734 BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);
8176 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,
8247 BNX2_WR(bp, PCI_COMMAND, reg);