Lines Matching refs:BNX2_RD
271 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);
313 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);
493 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
497 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
510 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
514 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
531 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
535 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
550 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
554 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
567 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
580 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
584 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
603 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
1327 val = BNX2_RD(bp, BNX2_EMAC_MODE);
1369 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);
1580 val = BNX2_RD(bp, BNX2_EMAC_STATUS);
2436 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
2465 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
2576 val = BNX2_RD(bp, BNX2_CTX_COMMAND);
2601 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
3360 (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3371 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3427 msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3475 BNX2_RD(bp, BNX2_HC_COMMAND);
3975 val = BNX2_RD(bp, BNX2_EMAC_MODE);
4010 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
4049 val = BNX2_RD(bp, BNX2_EMAC_MODE);
4054 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
4104 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4127 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4146 val = BNX2_RD(bp, BNX2_MISC_CFG);
4159 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4175 val = BNX2_RD(bp, BNX2_MISC_CFG);
4185 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4196 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4232 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4274 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4276 __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));
4323 if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4345 val = BNX2_RD(bp, BNX2_NVM_CFG1);
4771 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4774 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4777 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4781 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4812 val = BNX2_RD(bp, BNX2_MISC_ID);
4816 BNX2_RD(bp, BNX2_MISC_COMMAND);
4842 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4857 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);
4926 val = BNX2_RD(bp, BNX2_TDMA_CONFIG);
4961 val = BNX2_RD(bp, BNX2_MQ_CONFIG);
4980 val = BNX2_RD(bp, BNX2_TBDR_CONFIG);
5107 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5115 BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5119 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);
5255 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);
5855 BNX2_RD(bp, BNX2_HC_COMMAND);
5881 BNX2_RD(bp, BNX2_HC_COMMAND);
6030 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
6034 BNX2_RD(bp, BNX2_HC_COMMAND);
6037 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
6279 BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);
6524 BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);
6533 while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &
6537 cid = BNX2_RD(bp, BNX2_TBDC_CID);
6538 bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);
6539 valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);
6560 BNX2_RD(bp, BNX2_EMAC_TX_STATUS),
6561 BNX2_RD(bp, BNX2_EMAC_RX_STATUS));
6563 BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6565 BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6568 BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
7099 *p++ = BNX2_RD(bp, offset);
7715 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);
7946 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7986 reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);
7992 clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
8180 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);
8245 reg = BNX2_RD(bp, PCI_COMMAND);
8409 !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {