Lines Matching refs:val
42 u32 val, u32 off)
44 bcm_writel(val, priv->base + off);
56 u32 val, u32 off)
58 bcm_writel(val, priv->base + off);
67 u16 val, u32 off)
69 bcm_writew(val, priv->base + off);
78 u8 val, u32 off)
80 bcm_writeb(val, priv->base + off);
91 u32 val, u32 off)
93 bcm_writel(val, bcm_enet_shared_base[0] + off);
103 u32 val, u32 off, int chan)
105 bcm_writel(val, bcm_enet_shared_base[1] +
115 u32 val, u32 off, int chan)
117 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
151 u32 tmp, val;
161 val = enet_readl(priv, ENET_MIIDATA_REG);
162 val &= 0xffff;
163 return val;
649 u32 val;
655 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
657 enet_writel(priv, val, ENET_PML_REG(0));
659 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
660 val |= ENET_PMH_DATAVALID_MASK;
661 enet_writel(priv, val, ENET_PMH_REG(0));
673 u32 val;
678 val = enet_readl(priv, ENET_RXCFG_REG);
681 val |= ENET_RXCFG_PROMISC_MASK;
683 val &= ~ENET_RXCFG_PROMISC_MASK;
688 val |= ENET_RXCFG_ALLMCAST_MASK;
690 val &= ~ENET_RXCFG_ALLMCAST_MASK;
694 if (val & ENET_RXCFG_ALLMCAST_MASK) {
695 enet_writel(priv, val, ENET_RXCFG_REG);
722 enet_writel(priv, val, ENET_RXCFG_REG);
730 u32 val;
732 val = enet_readl(priv, ENET_TXCTL_REG);
734 val |= ENET_TXCTL_FD_MASK;
736 val &= ~ENET_TXCTL_FD_MASK;
737 enet_writel(priv, val, ENET_TXCTL_REG);
745 u32 val;
748 val = enet_readl(priv, ENET_RXCFG_REG);
750 val |= ENET_RXCFG_ENFLOW_MASK;
752 val &= ~ENET_RXCFG_ENFLOW_MASK;
753 enet_writel(priv, val, ENET_RXCFG_REG);
759 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
761 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
763 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
764 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
861 u32 val;
1024 val = priv->rx_ring_size / 3;
1025 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1026 val = (priv->rx_ring_size * 2) / 3;
1027 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1037 val = enet_readl(priv, ENET_CTL_REG);
1038 val |= ENET_CTL_ENABLE_MASK;
1039 enet_writel(priv, val, ENET_CTL_REG);
1118 u32 val;
1120 val = enet_readl(priv, ENET_CTL_REG);
1121 val |= ENET_CTL_DISABLE_MASK;
1122 enet_writel(priv, val, ENET_CTL_REG);
1126 u32 val;
1128 val = enet_readl(priv, ENET_CTL_REG);
1129 if (!(val & ENET_CTL_DISABLE_MASK))
1146 u32 val;
1148 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1149 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1342 u32 val;
1349 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1353 *(u64 *)p += val;
1355 *(u32 *)p += val;
1637 u32 val;
1644 val = ENET_CTL_SRESET_MASK;
1645 enet_writel(priv, val, ENET_CTL_REG);
1650 val = enet_readl(priv, ENET_CTL_REG);
1651 if (!(val & ENET_CTL_SRESET_MASK))
1657 val = enet_readl(priv, ENET_CTL_REG);
1659 val |= ENET_CTL_EPHYSEL_MASK;
1661 val &= ~ENET_CTL_EPHYSEL_MASK;
1662 enet_writel(priv, val, ENET_CTL_REG);
1669 val = enet_readl(priv, ENET_MIBCTL_REG);
1670 val |= ENET_MIBCTL_RDCLEAR_MASK;
1671 enet_writel(priv, val, ENET_MIBCTL_REG);
1983 int val, j, up, advertise, lpa, speed, duplex, media;
1996 val = bcmenet_sw_mdio_read(priv, external_phy,
1999 if (val == 0xffff)
2002 up = (val & BMSR_LSTATUS) ? 1 : 0;
2035 if (val & BMSR_ESTATEN) {
2081 u32 val;
2164 val = enetsw_readb(priv, ENETSW_GMCR_REG);
2165 val |= ENETSW_GMCR_RST_MIB_MASK;
2166 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2168 val &= ~ENETSW_GMCR_RST_MIB_MASK;
2169 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2173 val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2174 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2175 enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2178 val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2179 val |= ENETSW_SWMODE_FWD_EN_MASK;
2180 enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2217 val = priv->rx_ring_size / 3;
2218 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2219 val = (priv->rx_ring_size * 2) / 3;
2220 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2418 int val)
2424 phy_id, location, val);