Lines Matching refs:val
170 unsigned long reg, unsigned long val)
172 ssb_write32(bp->sdev, reg, val);
181 u32 val = br32(bp, reg);
183 if (clear && !(val & bit))
185 if (!clear && (val & bit))
201 u32 val;
208 val = br32(bp, B44_CAM_DATA_LO);
210 data[2] = (val >> 24) & 0xFF;
211 data[3] = (val >> 16) & 0xFF;
212 data[4] = (val >> 8) & 0xFF;
213 data[5] = (val >> 0) & 0xFF;
215 val = br32(bp, B44_CAM_DATA_HI);
217 data[0] = (val >> 8) & 0xFF;
218 data[1] = (val >> 0) & 0xFF;
223 u32 val;
225 val = ((u32) data[2]) << 24;
226 val |= ((u32) data[3]) << 16;
227 val |= ((u32) data[4]) << 8;
228 val |= ((u32) data[5]) << 0;
229 bw32(bp, B44_CAM_DATA_LO, val);
230 val = (CAM_DATA_HI_VALID |
233 bw32(bp, B44_CAM_DATA_HI, val);
257 static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
268 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
273 static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
281 (val & MDIO_DATA_DATA)));
285 static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
290 return __b44_readphy(bp, bp->phy_addr, reg, val);
293 static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
298 return __b44_writephy(bp, bp->phy_addr, reg, val);
304 u32 val;
306 int rc = __b44_readphy(bp, phy_id, location, &val);
309 return val;
313 int val)
316 __b44_writephy(bp, phy_id, location, val);
321 u32 val;
323 int rc = __b44_readphy(bp, phy_id, location, &val);
326 return val;
330 u16 val)
333 return __b44_writephy(bp, phy_id, location, val);
338 u32 val;
347 err = b44_readphy(bp, MII_BMCR, &val);
349 if (val & BMCR_RESET) {
360 u32 val;
365 val = br32(bp, B44_RXCONFIG);
367 val |= RXCONFIG_FLOW;
369 val &= ~RXCONFIG_FLOW;
370 bw32(bp, B44_RXCONFIG, val);
372 val = br32(bp, B44_MAC_FLOW);
374 val |= (MAC_FLOW_PAUSE_ENAB |
377 val &= ~MAC_FLOW_PAUSE_ENAB;
378 bw32(bp, B44_MAC_FLOW, val);
405 u32 val;
416 err = __b44_readphy(bp, 0, MII_BMCR, &val);
419 if (!(val & BMCR_ISOLATE))
421 val &= ~BMCR_ISOLATE;
422 err = __b44_writephy(bp, 0, MII_BMCR, val);
438 u32 val;
445 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
448 val & MII_ALEDCTRL_ALLMSK)) != 0)
450 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
453 val | MII_TLEDCTRL_ENABLE)) != 0)
503 u64 *val;
505 val = &bp->hw_stats.tx_good_octets;
509 *val++ += br32(bp, reg);
513 *val++ += br32(bp, reg);
541 u32 val = br32(bp, B44_TX_CTRL);
543 val |= TX_CTRL_DUPLEX;
545 val &= ~TX_CTRL_DUPLEX;
546 bw32(bp, B44_TX_CTRL, val);
567 u32 val = br32(bp, B44_TX_CTRL);
571 val |= TX_CTRL_DUPLEX;
573 val &= ~TX_CTRL_DUPLEX;
574 bw32(bp, B44_TX_CTRL, val);
1333 u32 val = br32(bp, B44_DEVCTRL);
1335 if (val & DEVCTRL_EPR) {
1336 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1366 u32 val;
1369 val = br32(bp, B44_CAM_CTRL);
1370 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1378 u32 val;
1390 val = br32(bp, B44_RXCONFIG);
1391 if (!(val & RXCONFIG_CAM_ABSENT))
1405 u32 val;
1441 val = br32(bp, B44_ENET_CTRL);
1442 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1545 u32 val;
1587 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1588 bw32(bp, B44_WKUP_LEN, val);
1591 val = br32(bp, B44_DEVCTRL);
1592 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1599 u16 val;
1603 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1604 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1613 u32 val;
1621 val = bp->dev->dev_addr[2] << 24 |
1625 bw32(bp, B44_ADDR_LO, val);
1627 val = bp->dev->dev_addr[0] << 8 |
1629 bw32(bp, B44_ADDR_HI, val);
1631 val = br32(bp, B44_DEVCTRL);
1632 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1737 u32 val;
1739 val = br32(bp, B44_RXCONFIG);
1740 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1741 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1742 val |= RXCONFIG_PROMISC;
1743 bw32(bp, B44_RXCONFIG, val);
1752 val |= RXCONFIG_ALLMULTI;
1759 bw32(bp, B44_RXCONFIG, val);
1760 val = br32(bp, B44_CAM_CTRL);
1761 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
2236 u32 val = br32(bp, B44_TX_CTRL);
2238 val |= TX_CTRL_DUPLEX;
2240 val &= ~TX_CTRL_DUPLEX;
2241 bw32(bp, B44_TX_CTRL, val);