Lines Matching refs:bw32
169 static inline void bw32(const struct b44 *bp,
203 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
229 bw32(bp, B44_CAM_DATA_LO, val);
233 bw32(bp, B44_CAM_DATA_HI, val);
234 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
241 bw32(bp, B44_IMASK, 0);
254 bw32(bp, B44_IMASK, bp->imask);
261 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
262 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
275 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
276 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
370 bw32(bp, B44_RXCONFIG, val);
378 bw32(bp, B44_MAC_FLOW, val);
546 bw32(bp, B44_TX_CTRL, val);
574 bw32(bp, B44_TX_CTRL, val);
645 bw32(bp, B44_GPTIMER, 0);
856 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
942 bw32(bp, B44_ISTAT, istat);
1037 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1039 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1268 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1287 bw32(bp, B44_RCV_LAZY, 0);
1288 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1290 bw32(bp, B44_DMATX_CTRL, 0);
1296 bw32(bp, B44_DMARX_CTRL, 0);
1311 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1317 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1329 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1336 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1352 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1364 bw32(bp, B44_CAM_CTRL, 0);
1370 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1414 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1415 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1421 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1422 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1424 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1426 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1429 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1430 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1431 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1433 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1435 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1438 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1442 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1505 bw32(bp, B44_FILT_ADDR, table_offset + i);
1506 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1588 bw32(bp, B44_WKUP_LEN, val);
1592 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1602 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1615 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1619 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1625 bw32(bp, B44_ADDR_LO, val);
1629 bw32(bp, B44_ADDR_HI, val);
1632 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1743 bw32(bp, B44_RXCONFIG, val);
1759 bw32(bp, B44_RXCONFIG, val);
1761 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
2241 bw32(bp, B44_TX_CTRL, val);