Lines Matching refs:val

48 	u32 val;
52 val = alx_read_mem32(hw, ALX_MDIO);
53 if (!(val & ALX_MDIO_BUSY))
64 u32 val, clk_sel;
75 val = dev << ALX_MDIO_EXTN_DEVAD_SHIFT |
77 alx_write_mem32(hw, ALX_MDIO_EXTN, val);
79 val = ALX_MDIO_SPRES_PRMBL | ALX_MDIO_START |
83 val = ALX_MDIO_SPRES_PRMBL |
88 alx_write_mem32(hw, ALX_MDIO, val);
93 val = alx_read_mem32(hw, ALX_MDIO);
94 *phy_data = ALX_GET_FIELD(val, ALX_MDIO_DATA);
101 u32 val, clk_sel;
109 val = dev << ALX_MDIO_EXTN_DEVAD_SHIFT |
111 alx_write_mem32(hw, ALX_MDIO_EXTN, val);
113 val = ALX_MDIO_SPRES_PRMBL |
118 val = ALX_MDIO_SPRES_PRMBL |
124 alx_write_mem32(hw, ALX_MDIO, val);
239 u32 val;
242 val = alx_read_mem32(hw, ALX_PHY_CTRL);
244 if ((val & ALX_PHY_CTRL_DSPRST_OUT) == 0)
247 val = alx_read_mem32(hw, ALX_DRV);
248 val = ALX_GET_FIELD(val, ALX_DRV_PHY);
249 if (ALX_DRV_PHY_UNKNOWN == val)
254 return val;
259 static bool alx_wait_reg(struct alx_hw *hw, u32 reg, u32 wait, u32 *val)
267 if (val)
268 *val = read;
293 u32 val;
300 if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_STAT | ALX_SLD_START, &val))
302 alx_write_mem32(hw, ALX_SLD, val | ALX_SLD_START);
309 val = alx_read_mem32(hw, ALX_EFLD);
310 if (val & (ALX_EFLD_F_EXIST | ALX_EFLD_E_EXIST)) {
312 ALX_EFLD_STAT | ALX_EFLD_START, &val))
314 alx_write_mem32(hw, ALX_EFLD, val | ALX_EFLD_START);
326 u32 val;
329 val = be32_to_cpu(get_unaligned((__be32 *)(addr + 2)));
330 alx_write_mem32(hw, ALX_STAD0, val);
331 val = be16_to_cpu(get_unaligned((__be16 *)addr));
332 alx_write_mem32(hw, ALX_STAD1, val);
337 u32 val, val2;
340 val = alx_read_mem32(hw, ALX_MISC3);
342 (val & ~ALX_MISC3_25M_BY_SW) |
348 val = alx_read_mem32(hw, ALX_MISC);
350 /* restore over current protection def-val,
351 * this val could be reset by MAC-RST
353 ALX_SET_FIELD(val, ALX_MISC_PSW_OCP, ALX_MISC_PSW_OCP_DEF);
354 /* a 0->1 change will update the internal val of osc */
355 val &= ~ALX_MISC_INTNLOSC_OPEN;
356 alx_write_mem32(hw, ALX_MISC, val);
357 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
364 val &= ~ALX_MISC_INTNLOSC_OPEN;
367 val &= ~ALX_MISC_ISO_EN;
369 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
370 alx_write_mem32(hw, ALX_MISC, val);
378 u32 rxq, txq, val;
392 val = alx_read_mem32(hw, ALX_MAC_STS);
393 if (!(val & ALX_MAC_STS_IDLE))
403 u32 val, pmctrl;
434 val = alx_read_mem32(hw, ALX_MASTER);
436 val | ALX_MASTER_DMA_MAC_RST | ALX_MASTER_OOB_DIS);
441 val = alx_read_mem32(hw, ALX_RFD_PIDX);
442 if (val == 0)
447 val = alx_read_mem32(hw, ALX_MASTER);
448 if ((val & ALX_MASTER_DMA_MAC_RST) == 0)
457 alx_write_mem32(hw, ALX_MASTER, val | ALX_MASTER_PCLKSEL_SRDS);
468 val = alx_read_mem32(hw, ALX_MISC3);
470 (val & ~ALX_MISC3_25M_BY_SW) |
472 val = alx_read_mem32(hw, ALX_MISC);
473 val &= ~ALX_MISC_INTNLOSC_OPEN;
475 val &= ~ALX_MISC_ISO_EN;
476 alx_write_mem32(hw, ALX_MISC, val);
482 val = alx_read_mem32(hw, ALX_SERDES);
484 val | ALX_SERDES_MACCLK_SLWDWN |
493 u32 val;
497 val = alx_read_mem32(hw, ALX_PHY_CTRL);
498 val &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_IDDQ |
501 val |= ALX_PHY_CTRL_RST_ANALOG;
503 val |= (ALX_PHY_CTRL_HIB_PULSE | ALX_PHY_CTRL_HIB_EN);
504 alx_write_mem32(hw, ALX_PHY_CTRL, val);
506 alx_write_mem32(hw, ALX_PHY_CTRL, val | ALX_PHY_CTRL_DSPRST_OUT);
519 val = alx_read_mem32(hw, ALX_LPI_CTRL);
520 alx_write_mem32(hw, ALX_LPI_CTRL, val & ~ALX_LPI_CTRL_EN);
563 u32 val;
574 val = alx_read_mem32(hw, ALX_WOL0);
577 val = alx_read_mem32(hw, ALX_PDLL_TRNS1);
578 alx_write_mem32(hw, ALX_PDLL_TRNS1, val & ~ALX_PDLL_TRNS1_D3PLLOFF_EN);
581 val = alx_read_mem32(hw, ALX_UE_SVRT);
582 val &= ~(ALX_UE_SVRT_DLPROTERR | ALX_UE_SVRT_FCPROTERR);
583 alx_write_mem32(hw, ALX_UE_SVRT, val);
586 val = alx_read_mem32(hw, ALX_MASTER);
588 if ((val & ALX_MASTER_WAKEN_25M) == 0 ||
589 (val & ALX_MASTER_PCLKSEL_SRDS) == 0)
591 val | ALX_MASTER_PCLKSEL_SRDS |
594 if ((val & ALX_MASTER_WAKEN_25M) == 0 ||
595 (val & ALX_MASTER_PCLKSEL_SRDS) != 0)
597 (val & ~ALX_MASTER_PCLKSEL_SRDS) |
725 u32 val;
729 val = alx_read_mem32(hw, ALX_DRV);
730 ALX_SET_FIELD(val, ALX_DRV_PHY, 0);
769 val |= ethadv_to_hw_cfg(hw, ethadv);
772 alx_write_mem32(hw, ALX_DRV, val);
933 u32 val, raw_mtu, max_payload;
948 val = alx_read_mem32(hw, ALX_MASTER);
949 val |= ALX_MASTER_IRQMOD2_EN |
952 alx_write_mem32(hw, ALX_MASTER, val);
967 val = (raw_mtu + 7) >> 3;
969 val = ALX_TXQ1_JUMBO_TSO_TH >> 3;
970 alx_write_mem32(hw, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN);
980 val = ALX_TXQ_TPD_BURSTPREF_DEF << ALX_TXQ0_TPD_BURSTPREF_SHIFT |
984 alx_write_mem32(hw, ALX_TXQ0, val);
985 val = ALX_TXQ_TPD_BURSTPREF_DEF << ALX_HQTPD_Q1_NUMPREF_SHIFT |
989 alx_write_mem32(hw, ALX_HQTPD, val);
992 val = alx_read_mem32(hw, ALX_SRAM5);
993 val = ALX_GET_FIELD(val, ALX_SRAM_RXF_LEN) << 3;
994 if (val > ALX_SRAM_RXF_LEN_8K) {
996 val = (val - ALX_RXQ2_RXF_FLOW_CTRL_RSVD) >> 3;
999 val = (val - ALX_MTU_STD_ALGN) >> 3;
1003 val << ALX_RXQ2_RXF_XON_THRESH_SHIFT);
1004 val = ALX_RXQ0_NUM_RFD_PREF_DEF << ALX_RXQ0_NUM_RFD_PREF_SHIFT |
1011 ALX_SET_FIELD(val, ALX_RXQ0_ASPM_THRESH,
1014 alx_write_mem32(hw, ALX_RXQ0, val);
1016 val = alx_read_mem32(hw, ALX_DMA);
1017 val = ALX_DMA_RORDER_MODE_OUT << ALX_DMA_RORDER_MODE_SHIFT |
1023 alx_write_mem32(hw, ALX_DMA, val);
1026 val = ALX_WRR_PRI_RESTRICT_NONE << ALX_WRR_PRI_SHIFT |
1031 alx_write_mem32(hw, ALX_WRR, val);
1036 u32 reg, val;
1041 val = mask ? PCI_MSIX_ENTRY_CTRL_MASKBIT : 0;
1043 alx_write_mem32(hw, reg, val);