Lines Matching defs:bmwrite
210 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )
245 bmwrite(dev, MIFCSR, 0);
249 bmwrite(dev, MIFCSR, 1);
252 bmwrite(dev, MIFCSR, 0);
254 bmwrite(dev, MIFCSR, 1);
266 bmwrite(dev, MIFCSR, b);
268 bmwrite(dev, MIFCSR, b|1);
278 bmwrite(dev, MIFCSR, 4);
283 bmwrite(dev, MIFCSR, 2);
285 bmwrite(dev, MIFCSR, 1);
288 bmwrite(dev, MIFCSR, 4);
296 bmwrite(dev, MIFCSR, 4);
316 bmwrite(dev, RXRST, RxResetValue);
317 bmwrite(dev, TXRST, TxResetBit);
329 bmwrite(dev, XCVRIF, regValue);
333 bmwrite(dev, RSEED, (unsigned short)0x1968);
337 bmwrite(dev, XIFC, regValue);
342 bmwrite(dev, NCCNT, 0);
343 bmwrite(dev, NTCNT, 0);
344 bmwrite(dev, EXCNT, 0);
345 bmwrite(dev, LTCNT, 0);
348 bmwrite(dev, FRCNT, 0);
349 bmwrite(dev, LECNT, 0);
350 bmwrite(dev, AECNT, 0);
351 bmwrite(dev, FECNT, 0);
352 bmwrite(dev, RXCV, 0);
355 bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
357 bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
358 bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
361 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
362 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
364 //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
369 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
370 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
371 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
372 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
375 bmwrite(dev, MADD0, *pWord16++);
376 bmwrite(dev, MADD1, *pWord16++);
377 bmwrite(dev, MADD2, *pWord16);
379 bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
381 bmwrite(dev, INTDISABLE, EnableNormal);
388 bmwrite(dev, INTDISABLE, DisableAll);
394 bmwrite(dev, INTDISABLE, EnableNormal);
410 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
414 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
478 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
480 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
481 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
537 bmwrite(dev, MADD0, *pWord16++);
538 bmwrite(dev, MADD1, *pWord16++);
539 bmwrite(dev, MADD2, *pWord16);
904 bmwrite(dev, RXCFG, rx_cfg);
921 bmwrite(dev, RXRST, RxResetValue);
922 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
923 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
924 bmwrite(dev, RXCFG, rx_cfg );
931 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
932 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
933 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
934 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
988 bmwrite(dev, RXCFG, rx_cfg);
1018 bmwrite(dev, BHASH0, 0xffff);
1019 bmwrite(dev, BHASH1, 0xffff);
1020 bmwrite(dev, BHASH2, 0xffff);
1021 bmwrite(dev, BHASH3, 0xffff);
1025 bmwrite(dev, RXCFG, rx_cfg);
1031 bmwrite(dev, RXCFG, rx_cfg);
1038 bmwrite(dev, BHASH0, hash_table[0]);
1039 bmwrite(dev, BHASH1, hash_table[1]);
1040 bmwrite(dev, BHASH2, hash_table[2]);
1041 bmwrite(dev, BHASH3, hash_table[3]);
1093 bmwrite(dev, SROMCSR, ChipSelect | Clk);
1100 bmwrite(dev, SROMCSR, ChipSelect);
1114 bmwrite(dev, SROMCSR, data | ChipSelect );
1117 bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
1120 bmwrite(dev, SROMCSR, data | ChipSelect);
1128 bmwrite(dev, SROMCSR, 0);
1156 bmwrite(dev, SROMCSR, 0);
1207 bmwrite(dev, INTDISABLE, EnableNormal);
1286 bmwrite(dev, INTDISABLE, DisableAll);
1294 bmwrite(dev, INTDISABLE, DisableAll);
1399 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1402 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1404 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
1494 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1496 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1533 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
1535 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );