Lines Matching refs:pdata
125 static int xgbe_config_multi_msi(struct xgbe_prv_data *pdata)
132 vector_count += max(pdata->rx_ring_count,
133 pdata->tx_ring_count);
135 ret = pci_alloc_irq_vectors(pdata->pcidev, XGBE_MSI_MIN_COUNT,
138 dev_info(pdata->dev, "multi MSI/MSI-X enablement failed\n");
142 pdata->isr_as_tasklet = 1;
143 pdata->irq_count = ret;
145 pdata->dev_irq = pci_irq_vector(pdata->pcidev, 0);
146 pdata->ecc_irq = pci_irq_vector(pdata->pcidev, 1);
147 pdata->i2c_irq = pci_irq_vector(pdata->pcidev, 2);
148 pdata->an_irq = pci_irq_vector(pdata->pcidev, 3);
151 pdata->channel_irq[j] = pci_irq_vector(pdata->pcidev, i);
152 pdata->channel_irq_count = j;
154 pdata->per_channel_irq = 1;
155 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
157 if (netif_msg_probe(pdata))
158 dev_dbg(pdata->dev, "multi %s interrupts enabled\n",
159 pdata->pcidev->msix_enabled ? "MSI-X" : "MSI");
164 static int xgbe_config_irqs(struct xgbe_prv_data *pdata)
168 ret = xgbe_config_multi_msi(pdata);
172 ret = pci_alloc_irq_vectors(pdata->pcidev, 1, 1,
175 dev_info(pdata->dev, "single IRQ enablement failed\n");
179 pdata->isr_as_tasklet = pdata->pcidev->msi_enabled ? 1 : 0;
180 pdata->irq_count = 1;
181 pdata->channel_irq_count = 1;
183 pdata->dev_irq = pci_irq_vector(pdata->pcidev, 0);
184 pdata->ecc_irq = pci_irq_vector(pdata->pcidev, 0);
185 pdata->i2c_irq = pci_irq_vector(pdata->pcidev, 0);
186 pdata->an_irq = pci_irq_vector(pdata->pcidev, 0);
188 if (netif_msg_probe(pdata))
189 dev_dbg(pdata->dev, "single %s interrupt enabled\n",
190 pdata->pcidev->msi_enabled ? "MSI" : "legacy");
193 if (netif_msg_probe(pdata)) {
196 dev_dbg(pdata->dev, " dev irq=%d\n", pdata->dev_irq);
197 dev_dbg(pdata->dev, " ecc irq=%d\n", pdata->ecc_irq);
198 dev_dbg(pdata->dev, " i2c irq=%d\n", pdata->i2c_irq);
199 dev_dbg(pdata->dev, " an irq=%d\n", pdata->an_irq);
200 for (i = 0; i < pdata->channel_irq_count; i++)
201 dev_dbg(pdata->dev, " dma%u irq=%d\n",
202 i, pdata->channel_irq[i]);
210 struct xgbe_prv_data *pdata;
219 pdata = xgbe_alloc_pdata(dev);
220 if (IS_ERR(pdata)) {
221 ret = PTR_ERR(pdata);
225 pdata->pcidev = pdev;
226 pci_set_drvdata(pdev, pdata);
229 pdata->vdata = (struct xgbe_version_data *)id->driver_data;
252 pdata->xgmac_regs = iomap_table[XGBE_XGMAC_BAR];
253 if (!pdata->xgmac_regs) {
258 pdata->xprop_regs = pdata->xgmac_regs + XGBE_MAC_PROP_OFFSET;
259 pdata->xi2c_regs = pdata->xgmac_regs + XGBE_I2C_CTRL_OFFSET;
260 if (netif_msg_probe(pdata)) {
261 dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs);
262 dev_dbg(dev, "xprop_regs = %p\n", pdata->xprop_regs);
263 dev_dbg(dev, "xi2c_regs = %p\n", pdata->xi2c_regs);
266 pdata->xpcs_regs = iomap_table[XGBE_XPCS_BAR];
267 if (!pdata->xpcs_regs) {
272 if (netif_msg_probe(pdata))
273 dev_dbg(dev, "xpcs_regs = %p\n", pdata->xpcs_regs);
279 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
280 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
282 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
283 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
288 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
289 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
290 pdata->xpcs_window <<= 6;
291 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
292 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
293 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
294 if (netif_msg_probe(pdata)) {
296 pdata->xpcs_window_def_reg);
298 pdata->xpcs_window_sel_reg);
300 pdata->xpcs_window);
302 pdata->xpcs_window_size);
304 pdata->xpcs_window_mask);
310 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
313 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
314 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
315 pdata->mac_addr[0] = ma_lo & 0xff;
316 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
317 pdata->mac_addr[2] = (ma_lo >> 16) & 0xff;
318 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
319 pdata->mac_addr[4] = ma_hi & 0xff;
320 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
322 !is_valid_ether_addr(pdata->mac_addr)) {
329 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
330 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
333 pdata->coherent = 1;
334 pdata->arcr = XGBE_DMA_PCI_ARCR;
335 pdata->awcr = XGBE_DMA_PCI_AWCR;
336 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
339 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
340 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
341 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
342 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
343 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
344 if (netif_msg_probe(pdata)) {
345 dev_dbg(dev, "port property 0 = %#010x\n", pdata->pp0);
346 dev_dbg(dev, "port property 1 = %#010x\n", pdata->pp1);
347 dev_dbg(dev, "port property 2 = %#010x\n", pdata->pp2);
348 dev_dbg(dev, "port property 3 = %#010x\n", pdata->pp3);
349 dev_dbg(dev, "port property 4 = %#010x\n", pdata->pp4);
353 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
355 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
357 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
359 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
361 if (netif_msg_probe(pdata)) {
363 pdata->tx_max_channel_count,
364 pdata->rx_max_channel_count);
366 pdata->tx_max_q_count, pdata->rx_max_q_count);
370 xgbe_set_counts(pdata);
373 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
375 pdata->tx_max_fifo_size *= 16384;
376 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
377 pdata->vdata->tx_max_fifo_size);
378 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
380 pdata->rx_max_fifo_size *= 16384;
381 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
382 pdata->vdata->rx_max_fifo_size);
383 if (netif_msg_probe(pdata))
385 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
388 ret = xgbe_config_irqs(pdata);
393 ret = xgbe_config_netdev(pdata);
397 netdev_notice(pdata->netdev, "net device enabled\n");
402 pci_free_irq_vectors(pdata->pcidev);
405 xgbe_free_pdata(pdata);
415 struct xgbe_prv_data *pdata = pci_get_drvdata(pdev);
417 xgbe_deconfig_netdev(pdata);
419 pci_free_irq_vectors(pdata->pcidev);
421 xgbe_free_pdata(pdata);
426 struct xgbe_prv_data *pdata = dev_get_drvdata(dev);
427 struct net_device *netdev = pdata->netdev;
433 pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
434 pdata->lpm_ctrl |= MDIO_CTRL1_LPOWER;
435 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
442 struct xgbe_prv_data *pdata = dev_get_drvdata(dev);
443 struct net_device *netdev = pdata->netdev;
446 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
448 pdata->lpm_ctrl &= ~MDIO_CTRL1_LPOWER;
449 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
457 schedule_work(&pdata->restart_work);