Lines Matching refs:reg
149 int reg;
151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
152 reg &= ~XGBE_AN_CL37_INT_MASK;
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
158 int reg;
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
161 reg &= ~XGBE_AN_CL37_INT_MASK;
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
164 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
165 reg &= ~XGBE_PCS_CL37_BP;
166 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
171 int reg;
173 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
174 reg |= XGBE_PCS_CL37_BP;
175 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
178 reg |= XGBE_AN_CL37_INT_MASK;
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
354 unsigned int reg;
356 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
357 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
360 reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
363 reg |= MDIO_VEND2_CTRL1_AN_RESTART;
365 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
387 unsigned int reg;
390 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
391 reg &= ~XGBE_KR_TRAINING_ENABLE;
392 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
395 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
396 reg &= ~MDIO_AN_CTRL1_ENABLE;
399 reg |= MDIO_AN_CTRL1_ENABLE;
402 reg |= MDIO_AN_CTRL1_RESTART;
404 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
472 unsigned int ad_reg, lp_reg, reg;
484 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
485 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
487 reg |= pdata->fec_ability;
489 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
495 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
496 reg |= XGBE_KR_TRAINING_ENABLE;
497 reg |= XGBE_KR_TRAINING_START;
498 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
531 unsigned int reg, ad_reg, lp_reg;
534 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
538 if (!(reg & link_support))
645 unsigned int reg;
651 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
652 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
653 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
657 reg &= ~XGBE_AN_CL37_INT_MASK;
658 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
950 unsigned int reg;
955 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
957 reg |= 0x100;
959 reg &= ~0x100;
962 reg |= 0x80;
964 reg &= ~0x80;
967 reg |= XGBE_AN_CL37_FD_MASK;
968 reg &= ~XGBE_AN_CL37_HD_MASK;
970 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
973 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
974 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;
975 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;
979 reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
982 reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
988 reg |= XGBE_AN_CL37_MII_CTRL_8BIT;
990 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
999 unsigned int reg;
1004 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1006 reg |= 0xc000;
1008 reg &= ~0xc000;
1010 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
1013 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1015 reg |= 0x80;
1017 reg &= ~0x80;
1021 reg |= 0x20;
1023 reg &= ~0x20;
1025 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
1028 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1030 reg |= 0x400;
1032 reg &= ~0x400;
1035 reg |= 0x800;
1037 reg &= ~0x800;
1040 reg &= ~XGBE_XNP_NP_EXCHANGE;
1042 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);