Lines Matching refs:pdata
129 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
132 if (!pdata->phy_if.phy_impl.module_eeprom)
135 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data);
138 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
141 if (!pdata->phy_if.phy_impl.module_info)
144 return pdata->phy_if.phy_impl.module_info(pdata, modinfo);
147 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
156 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
164 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
166 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
169 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
173 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
175 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
182 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
184 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
187 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
189 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
192 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
194 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
197 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
199 switch (pdata->an_mode) {
202 xgbe_an73_enable_interrupts(pdata);
206 xgbe_an37_enable_interrupts(pdata);
213 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
215 xgbe_an73_clear_interrupts(pdata);
216 xgbe_an37_clear_interrupts(pdata);
219 static void xgbe_kr_mode(struct xgbe_prv_data *pdata)
222 pdata->hw_if.set_speed(pdata, SPEED_10000);
225 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
228 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
231 pdata->hw_if.set_speed(pdata, SPEED_2500);
234 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
237 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
240 pdata->hw_if.set_speed(pdata, SPEED_1000);
243 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
246 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
249 if (pdata->kr_redrv)
250 return xgbe_kr_mode(pdata);
253 pdata->hw_if.set_speed(pdata, SPEED_10000);
256 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
259 static void xgbe_x_mode(struct xgbe_prv_data *pdata)
262 pdata->hw_if.set_speed(pdata, SPEED_1000);
265 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
268 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
271 pdata->hw_if.set_speed(pdata, SPEED_1000);
274 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
277 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
280 pdata->hw_if.set_speed(pdata, SPEED_1000);
283 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
286 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
288 return pdata->phy_if.phy_impl.cur_mode(pdata);
291 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
293 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
296 static void xgbe_change_mode(struct xgbe_prv_data *pdata,
301 xgbe_kx_1000_mode(pdata);
304 xgbe_kx_2500_mode(pdata);
307 xgbe_kr_mode(pdata);
310 xgbe_sgmii_100_mode(pdata);
313 xgbe_sgmii_1000_mode(pdata);
316 xgbe_x_mode(pdata);
319 xgbe_sfi_mode(pdata);
324 netif_dbg(pdata, link, pdata->netdev,
329 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
331 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
334 static bool xgbe_set_mode(struct xgbe_prv_data *pdata,
337 if (mode == xgbe_cur_mode(pdata))
340 xgbe_change_mode(pdata, mode);
345 static bool xgbe_use_mode(struct xgbe_prv_data *pdata,
348 return pdata->phy_if.phy_impl.use_mode(pdata, mode);
351 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
356 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
365 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
368 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
370 xgbe_an37_enable_interrupts(pdata);
371 xgbe_an37_set(pdata, true, true);
373 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n");
376 static void xgbe_an37_disable(struct xgbe_prv_data *pdata)
378 xgbe_an37_set(pdata, false, false);
379 xgbe_an37_disable_interrupts(pdata);
381 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n");
384 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable,
390 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
392 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
395 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
404 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
407 static void xgbe_an73_restart(struct xgbe_prv_data *pdata)
409 xgbe_an73_enable_interrupts(pdata);
410 xgbe_an73_set(pdata, true, true);
412 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n");
415 static void xgbe_an73_disable(struct xgbe_prv_data *pdata)
417 xgbe_an73_set(pdata, false, false);
418 xgbe_an73_disable_interrupts(pdata);
420 pdata->an_start = 0;
422 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n");
425 static void xgbe_an_restart(struct xgbe_prv_data *pdata)
427 if (pdata->phy_if.phy_impl.an_pre)
428 pdata->phy_if.phy_impl.an_pre(pdata);
430 switch (pdata->an_mode) {
433 xgbe_an73_restart(pdata);
437 xgbe_an37_restart(pdata);
444 static void xgbe_an_disable(struct xgbe_prv_data *pdata)
446 if (pdata->phy_if.phy_impl.an_post)
447 pdata->phy_if.phy_impl.an_post(pdata);
449 switch (pdata->an_mode) {
452 xgbe_an73_disable(pdata);
456 xgbe_an37_disable(pdata);
463 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata)
465 xgbe_an73_disable(pdata);
466 xgbe_an37_disable(pdata);
469 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata,
477 if (!xgbe_in_kr_mode(pdata))
481 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
482 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
484 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
487 reg |= pdata->fec_ability;
489 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
492 if (pdata->phy_if.phy_impl.kr_training_pre)
493 pdata->phy_if.phy_impl.kr_training_pre(pdata);
495 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
498 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
499 pdata->kr_start_time = jiffies;
501 netif_dbg(pdata, link, pdata->netdev,
504 if (pdata->phy_if.phy_impl.kr_training_post)
505 pdata->phy_if.phy_impl.kr_training_post(pdata);
510 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata,
520 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
521 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
522 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
527 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata,
534 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
537 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
542 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
543 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
547 ? xgbe_an73_tx_xnp(pdata, state)
548 : xgbe_an73_tx_training(pdata, state);
551 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata,
557 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
558 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
562 ? xgbe_an73_tx_xnp(pdata, state)
563 : xgbe_an73_tx_training(pdata, state);
566 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata)
572 if (!pdata->an_start) {
573 pdata->an_start = jiffies;
575 an_timeout = pdata->an_start +
579 pdata->kr_state = XGBE_RX_BPA;
580 pdata->kx_state = XGBE_RX_BPA;
582 pdata->an_start = jiffies;
584 netif_dbg(pdata, link, pdata->netdev,
589 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
590 : &pdata->kx_state;
594 ret = xgbe_an73_rx_bpa(pdata, state);
598 ret = xgbe_an73_rx_xnp(pdata, state);
608 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
610 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
613 if (xgbe_in_kr_mode(pdata)) {
614 pdata->kr_state = XGBE_RX_ERROR;
620 if (pdata->kx_state != XGBE_RX_BPA)
623 pdata->kx_state = XGBE_RX_ERROR;
628 if (pdata->kr_state != XGBE_RX_BPA)
632 xgbe_an_disable(pdata);
634 xgbe_switch_mode(pdata);
636 pdata->an_result = XGBE_AN_READY;
638 xgbe_an_restart(pdata);
643 static void xgbe_an37_isr(struct xgbe_prv_data *pdata)
648 xgbe_an37_disable_interrupts(pdata);
651 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
652 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
653 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
655 if (pdata->an_int) {
658 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
660 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
663 xgbe_an37_enable_interrupts(pdata);
666 if (pdata->vdata->irq_reissue_support)
667 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
671 static void xgbe_an73_isr(struct xgbe_prv_data *pdata)
674 xgbe_an73_disable_interrupts(pdata);
677 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
679 if (pdata->an_int) {
681 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
683 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
686 xgbe_an73_enable_interrupts(pdata);
689 if (pdata->vdata->irq_reissue_support)
690 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
696 struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_an);
698 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
700 switch (pdata->an_mode) {
703 xgbe_an73_isr(pdata);
707 xgbe_an37_isr(pdata);
716 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
718 if (pdata->isr_as_tasklet)
719 tasklet_schedule(&pdata->tasklet_an);
721 xgbe_an_isr_task(&pdata->tasklet_an);
726 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata)
728 xgbe_an_isr_task(&pdata->tasklet_an);
735 struct xgbe_prv_data *pdata = container_of(work,
742 flush_work(&pdata->an_work);
743 queue_work(pdata->an_workqueue, &pdata->an_work);
766 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
768 enum xgbe_an cur_state = pdata->an_state;
770 if (!pdata->an_int)
773 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
774 pdata->an_state = XGBE_AN_COMPLETE;
775 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
778 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
779 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
780 pdata->an_state = XGBE_AN_NO_LINK;
783 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n",
784 xgbe_state_as_string(pdata->an_state));
786 cur_state = pdata->an_state;
788 switch (pdata->an_state) {
793 netif_dbg(pdata, link, pdata->netdev,
801 pdata->an_state = XGBE_AN_ERROR;
804 if (pdata->an_state == XGBE_AN_ERROR) {
805 netdev_err(pdata->netdev,
809 pdata->an_int = 0;
810 xgbe_an37_clear_interrupts(pdata);
813 if (pdata->an_state >= XGBE_AN_COMPLETE) {
814 pdata->an_result = pdata->an_state;
815 pdata->an_state = XGBE_AN_READY;
817 if (pdata->phy_if.phy_impl.an_post)
818 pdata->phy_if.phy_impl.an_post(pdata);
820 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n",
821 xgbe_state_as_string(pdata->an_result));
824 xgbe_an37_enable_interrupts(pdata);
827 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
829 enum xgbe_an cur_state = pdata->an_state;
831 if (!pdata->an_int)
835 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
836 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
837 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
838 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
839 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
840 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
841 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
842 pdata->an_state = XGBE_AN_COMPLETE;
843 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
845 pdata->an_state = XGBE_AN_ERROR;
849 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n",
850 xgbe_state_as_string(pdata->an_state));
852 cur_state = pdata->an_state;
854 switch (pdata->an_state) {
856 pdata->an_supported = 0;
860 pdata->an_state = xgbe_an73_page_received(pdata);
861 pdata->an_supported++;
865 pdata->an_supported = 0;
866 pdata->parallel_detect = 0;
867 pdata->an_state = xgbe_an73_incompat_link(pdata);
871 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
872 netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
873 pdata->an_supported ? "Auto negotiation"
881 pdata->an_state = XGBE_AN_ERROR;
884 if (pdata->an_state == XGBE_AN_NO_LINK) {
885 pdata->an_int = 0;
886 xgbe_an73_clear_interrupts(pdata);
887 } else if (pdata->an_state == XGBE_AN_ERROR) {
888 netdev_err(pdata->netdev,
892 pdata->an_int = 0;
893 xgbe_an73_clear_interrupts(pdata);
896 if (pdata->an_state >= XGBE_AN_COMPLETE) {
897 pdata->an_result = pdata->an_state;
898 pdata->an_state = XGBE_AN_READY;
899 pdata->kr_state = XGBE_RX_BPA;
900 pdata->kx_state = XGBE_RX_BPA;
901 pdata->an_start = 0;
903 if (pdata->phy_if.phy_impl.an_post)
904 pdata->phy_if.phy_impl.an_post(pdata);
906 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n",
907 xgbe_state_as_string(pdata->an_result));
910 if (cur_state != pdata->an_state)
913 if (pdata->an_int)
916 xgbe_an73_enable_interrupts(pdata);
921 struct xgbe_prv_data *pdata = container_of(work,
925 mutex_lock(&pdata->an_mutex);
927 switch (pdata->an_mode) {
930 xgbe_an73_state_machine(pdata);
934 xgbe_an37_state_machine(pdata);
941 if (pdata->vdata->irq_reissue_support)
942 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
944 mutex_unlock(&pdata->an_mutex);
947 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
952 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
955 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
970 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
973 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
977 switch (pdata->an_mode) {
990 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
992 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
993 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
996 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
1001 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
1004 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1010 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
1013 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1025 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
1028 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1042 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
1044 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n");
1047 static void xgbe_an_init(struct xgbe_prv_data *pdata)
1050 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
1051 switch (pdata->an_mode) {
1054 xgbe_an73_init(pdata);
1058 xgbe_an37_init(pdata);
1065 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
1067 if (pdata->tx_pause && pdata->rx_pause)
1069 else if (pdata->rx_pause)
1071 else if (pdata->tx_pause)
1095 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1097 if (pdata->phy.link)
1098 netdev_info(pdata->netdev,
1100 xgbe_phy_speed_string(pdata->phy.speed),
1101 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1102 xgbe_phy_fc_string(pdata));
1104 netdev_info(pdata->netdev, "Link is Down\n");
1107 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1111 if (pdata->phy.link) {
1113 pdata->pause_autoneg = pdata->phy.pause_autoneg;
1115 if (pdata->tx_pause != pdata->phy.tx_pause) {
1117 pdata->tx_pause = pdata->phy.tx_pause;
1118 pdata->hw_if.config_tx_flow_control(pdata);
1121 if (pdata->rx_pause != pdata->phy.rx_pause) {
1123 pdata->rx_pause = pdata->phy.rx_pause;
1124 pdata->hw_if.config_rx_flow_control(pdata);
1128 if (pdata->phy_speed != pdata->phy.speed) {
1130 pdata->phy_speed = pdata->phy.speed;
1133 if (pdata->phy_link != pdata->phy.link) {
1135 pdata->phy_link = pdata->phy.link;
1137 } else if (pdata->phy_link) {
1139 pdata->phy_link = 0;
1140 pdata->phy_speed = SPEED_UNKNOWN;
1143 if (new_state && netif_msg_link(pdata))
1144 xgbe_phy_print_status(pdata);
1147 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1149 return pdata->phy_if.phy_impl.valid_speed(pdata, speed);
1152 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1156 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
1159 xgbe_an_disable(pdata);
1162 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1178 if (pdata->phy.duplex != DUPLEX_FULL)
1191 xgbe_change_mode(pdata, mode);
1193 xgbe_set_mode(pdata, mode);
1198 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata, bool set_mode)
1202 mutex_lock(&pdata->an_mutex);
1204 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1205 pdata->link_check = jiffies;
1207 ret = pdata->phy_if.phy_impl.an_config(pdata);
1211 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1212 ret = xgbe_phy_config_fixed(pdata);
1213 if (ret || !pdata->kr_redrv)
1216 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n");
1218 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
1222 disable_irq(pdata->an_irq);
1226 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1227 xgbe_set_mode(pdata, XGBE_MODE_KR);
1228 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1229 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1230 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1231 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1232 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1233 xgbe_set_mode(pdata, XGBE_MODE_SFI);
1234 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1235 xgbe_set_mode(pdata, XGBE_MODE_X);
1236 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1237 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1238 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1239 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1241 enable_irq(pdata->an_irq);
1248 xgbe_an_disable_all(pdata);
1251 xgbe_an_clear_interrupts_all(pdata);
1253 pdata->an_result = XGBE_AN_READY;
1254 pdata->an_state = XGBE_AN_READY;
1255 pdata->kr_state = XGBE_RX_BPA;
1256 pdata->kx_state = XGBE_RX_BPA;
1259 enable_irq(pdata->an_irq);
1261 xgbe_an_init(pdata);
1262 xgbe_an_restart(pdata);
1266 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1268 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1270 mutex_unlock(&pdata->an_mutex);
1275 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1277 return __xgbe_phy_config_aneg(pdata, true);
1280 static int xgbe_phy_reconfig_aneg(struct xgbe_prv_data *pdata)
1282 return __xgbe_phy_config_aneg(pdata, false);
1285 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1287 return (pdata->an_result == XGBE_AN_COMPLETE);
1290 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1296 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1298 if ((xgbe_cur_mode(pdata) == XGBE_MODE_KR) &&
1299 pdata->phy.autoneg == AUTONEG_ENABLE) {
1307 kr_time = pdata->kr_start_time +
1312 if (pdata->an_result == XGBE_AN_COMPLETE)
1317 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1318 xgbe_phy_config_aneg(pdata);
1322 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1324 return pdata->phy_if.phy_impl.an_outcome(pdata);
1327 static bool xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1329 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1334 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1335 mode = xgbe_cur_mode(pdata);
1337 mode = xgbe_phy_status_aneg(pdata);
1341 pdata->phy.speed = SPEED_100;
1346 pdata->phy.speed = SPEED_1000;
1349 pdata->phy.speed = SPEED_2500;
1353 pdata->phy.speed = SPEED_10000;
1357 pdata->phy.speed = SPEED_UNKNOWN;
1360 pdata->phy.duplex = DUPLEX_FULL;
1362 if (!xgbe_set_mode(pdata, mode))
1365 if (pdata->an_again)
1366 xgbe_phy_reconfig_aneg(pdata);
1371 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1376 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1377 netif_carrier_off(pdata->netdev);
1379 pdata->phy.link = 0;
1383 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1385 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1388 xgbe_phy_config_aneg(pdata);
1392 if (pdata->phy.link) {
1393 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1394 xgbe_check_link_timeout(pdata);
1398 if (xgbe_phy_status_result(pdata))
1401 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1402 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1404 netif_carrier_on(pdata->netdev);
1406 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1407 xgbe_check_link_timeout(pdata);
1413 xgbe_phy_status_result(pdata);
1415 netif_carrier_off(pdata->netdev);
1419 xgbe_phy_adjust_link(pdata);
1422 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1424 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1426 if (!pdata->phy_started)
1430 pdata->phy_started = 0;
1433 xgbe_an_disable_all(pdata);
1435 if (pdata->dev_irq != pdata->an_irq) {
1436 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1437 tasklet_kill(&pdata->tasklet_an);
1440 pdata->phy_if.phy_impl.stop(pdata);
1442 pdata->phy.link = 0;
1444 xgbe_phy_adjust_link(pdata);
1447 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1449 struct net_device *netdev = pdata->netdev;
1452 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1454 ret = pdata->phy_if.phy_impl.start(pdata);
1459 if (pdata->dev_irq != pdata->an_irq) {
1460 tasklet_setup(&pdata->tasklet_an, xgbe_an_isr_task);
1462 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1463 xgbe_an_isr, 0, pdata->an_name,
1464 pdata);
1474 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1475 xgbe_kr_mode(pdata);
1476 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1477 xgbe_kx_2500_mode(pdata);
1478 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1479 xgbe_kx_1000_mode(pdata);
1480 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1481 xgbe_sfi_mode(pdata);
1482 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1483 xgbe_x_mode(pdata);
1484 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1485 xgbe_sgmii_1000_mode(pdata);
1486 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1487 xgbe_sgmii_100_mode(pdata);
1494 pdata->phy_started = 1;
1496 xgbe_an_init(pdata);
1497 xgbe_an_enable_interrupts(pdata);
1499 return xgbe_phy_config_aneg(pdata);
1502 if (pdata->dev_irq != pdata->an_irq)
1503 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1506 pdata->phy_if.phy_impl.stop(pdata);
1511 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1515 ret = pdata->phy_if.phy_impl.reset(pdata);
1520 xgbe_an_disable_all(pdata);
1523 xgbe_an_clear_interrupts_all(pdata);
1528 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1530 struct device *dev = pdata->dev;
1535 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1537 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1539 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1541 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1543 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1545 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1548 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1550 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1553 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1556 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1559 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1562 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1567 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1569 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1589 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
1591 pdata->phy_if.phy_impl.exit(pdata);
1594 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
1596 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1599 mutex_init(&pdata->an_mutex);
1600 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1601 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1602 pdata->mdio_mmd = MDIO_MMD_PCS;
1605 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1607 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1611 ret = pdata->phy_if.phy_impl.init(pdata);
1618 pdata->phy.address = 0;
1621 pdata->phy.autoneg = AUTONEG_ENABLE;
1622 pdata->phy.speed = SPEED_UNKNOWN;
1623 pdata->phy.duplex = DUPLEX_UNKNOWN;
1625 pdata->phy.autoneg = AUTONEG_DISABLE;
1626 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1627 pdata->phy.duplex = DUPLEX_FULL;
1630 pdata->phy.link = 0;
1632 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1633 pdata->phy.tx_pause = pdata->tx_pause;
1634 pdata->phy.rx_pause = pdata->rx_pause;
1640 if (pdata->rx_pause) {
1645 if (pdata->tx_pause) {
1653 if (netif_msg_drv(pdata))
1654 xgbe_dump_phy_registers(pdata);