Lines Matching refs:pdata
139 static void xgbe_default_config(struct xgbe_prv_data *pdata)
143 pdata->blen = DMA_SBMR_BLEN_64;
144 pdata->pbl = DMA_PBL_128;
145 pdata->aal = 1;
146 pdata->rd_osr_limit = 8;
147 pdata->wr_osr_limit = 8;
148 pdata->tx_sf_mode = MTL_TSF_ENABLE;
149 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
150 pdata->tx_osp_mode = DMA_OSP_ENABLE;
151 pdata->rx_sf_mode = MTL_RSF_DISABLE;
152 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
153 pdata->pause_autoneg = 1;
154 pdata->tx_pause = 1;
155 pdata->rx_pause = 1;
156 pdata->phy_speed = SPEED_UNKNOWN;
157 pdata->power_down = 0;
162 static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
164 xgbe_init_function_ptrs_dev(&pdata->hw_if);
165 xgbe_init_function_ptrs_phy(&pdata->phy_if);
166 xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
167 xgbe_init_function_ptrs_desc(&pdata->desc_if);
169 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
174 struct xgbe_prv_data *pdata;
184 pdata = netdev_priv(netdev);
185 pdata->netdev = netdev;
186 pdata->dev = dev;
188 spin_lock_init(&pdata->lock);
189 spin_lock_init(&pdata->xpcs_lock);
190 mutex_init(&pdata->rss_mutex);
191 spin_lock_init(&pdata->tstamp_lock);
192 mutex_init(&pdata->i2c_mutex);
193 init_completion(&pdata->i2c_complete);
194 init_completion(&pdata->mdio_complete);
196 pdata->msg_enable = netif_msg_init(debug, default_msg_level);
198 set_bit(XGBE_DOWN, &pdata->dev_state);
199 set_bit(XGBE_STOPPED, &pdata->dev_state);
201 return pdata;
204 void xgbe_free_pdata(struct xgbe_prv_data *pdata)
206 struct net_device *netdev = pdata->netdev;
211 void xgbe_set_counts(struct xgbe_prv_data *pdata)
214 xgbe_init_all_fptrs(pdata);
217 xgbe_get_all_hw_features(pdata);
220 if (!pdata->tx_max_channel_count)
221 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
222 if (!pdata->rx_max_channel_count)
223 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
225 if (!pdata->tx_max_q_count)
226 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
227 if (!pdata->rx_max_q_count)
228 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
237 pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
238 pdata->hw_feat.tx_ch_cnt);
239 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
240 pdata->tx_max_channel_count);
241 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
242 pdata->tx_max_q_count);
244 pdata->tx_q_count = pdata->tx_ring_count;
246 pdata->rx_ring_count = min_t(unsigned int, num_online_cpus(),
247 pdata->hw_feat.rx_ch_cnt);
248 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
249 pdata->rx_max_channel_count);
251 pdata->rx_q_count = min_t(unsigned int, pdata->hw_feat.rx_q_cnt,
252 pdata->rx_max_q_count);
254 if (netif_msg_probe(pdata)) {
255 dev_dbg(pdata->dev, "TX/RX DMA channel count = %u/%u\n",
256 pdata->tx_ring_count, pdata->rx_ring_count);
257 dev_dbg(pdata->dev, "TX/RX hardware queue count = %u/%u\n",
258 pdata->tx_q_count, pdata->rx_q_count);
262 int xgbe_config_netdev(struct xgbe_prv_data *pdata)
264 struct net_device *netdev = pdata->netdev;
265 struct device *dev = pdata->dev;
268 netdev->irq = pdata->dev_irq;
269 netdev->base_addr = (unsigned long)pdata->xgmac_regs;
270 memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
273 pdata->tx_sec_period = jiffies;
274 pdata->tx_ded_period = jiffies;
275 pdata->rx_sec_period = jiffies;
276 pdata->rx_ded_period = jiffies;
277 pdata->desc_sec_period = jiffies;
278 pdata->desc_ded_period = jiffies;
281 ret = pdata->hw_if.exit(pdata);
288 xgbe_default_config(pdata);
292 DMA_BIT_MASK(pdata->hw_feat.dma_width));
299 if (!pdata->tx_max_fifo_size)
300 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
301 if (!pdata->rx_max_fifo_size)
302 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
306 pdata->tx_desc_count = XGBE_TX_DESC_CNT;
309 pdata->rx_desc_count = XGBE_RX_DESC_CNT;
312 if (pdata->channel_irq_count) {
313 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
314 pdata->channel_irq_count);
315 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
316 pdata->channel_irq_count);
318 if (netif_msg_probe(pdata))
319 dev_dbg(pdata->dev,
321 pdata->tx_ring_count, pdata->rx_ring_count);
325 netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key));
327 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
328 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
329 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
332 pdata->debugfs_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
333 ret = pdata->phy_if.phy_init(pdata);
356 if (pdata->hw_feat.rss)
359 if (pdata->hw_feat.vxn) {
383 pdata->netdev_features = netdev->features;
392 xgbe_init_rx_coalesce(pdata);
393 xgbe_init_tx_coalesce(pdata);
403 xgbe_ptp_register(pdata);
405 xgbe_debugfs_init(pdata);
407 netif_dbg(pdata, drv, pdata->netdev, "%u Tx software queues\n",
408 pdata->tx_ring_count);
409 netif_dbg(pdata, drv, pdata->netdev, "%u Rx software queues\n",
410 pdata->rx_ring_count);
415 void xgbe_deconfig_netdev(struct xgbe_prv_data *pdata)
417 struct net_device *netdev = pdata->netdev;
419 xgbe_debugfs_exit(pdata);
422 xgbe_ptp_unregister(pdata);
426 pdata->phy_if.phy_exit(pdata);
433 struct xgbe_prv_data *pdata = netdev_priv(netdev);
440 xgbe_debugfs_rename(pdata);