Lines Matching refs:pdata
127 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
129 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
132 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
140 rate = pdata->sysclk_rate;
155 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
163 rate = pdata->sysclk_rate;
178 static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata)
184 pbl = pdata->pbl;
186 if (pdata->pbl > 32) {
191 for (i = 0; i < pdata->channel_count; i++) {
192 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8,
195 if (pdata->channel[i]->tx_ring)
196 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR,
199 if (pdata->channel[i]->rx_ring)
200 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR,
207 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
211 for (i = 0; i < pdata->channel_count; i++) {
212 if (!pdata->channel[i]->tx_ring)
215 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP,
216 pdata->tx_osp_mode);
222 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
226 for (i = 0; i < pdata->rx_q_count; i++)
227 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
232 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
236 for (i = 0; i < pdata->tx_q_count; i++)
237 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
242 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
247 for (i = 0; i < pdata->rx_q_count; i++)
248 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
253 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
258 for (i = 0; i < pdata->tx_q_count; i++)
259 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
264 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
268 for (i = 0; i < pdata->channel_count; i++) {
269 if (!pdata->channel[i]->rx_ring)
272 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT,
273 pdata->rx_riwt);
279 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
284 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
288 for (i = 0; i < pdata->channel_count; i++) {
289 if (!pdata->channel[i]->rx_ring)
292 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ,
293 pdata->rx_buf_size);
297 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
301 for (i = 0; i < pdata->channel_count; i++) {
302 if (!pdata->channel[i]->tx_ring)
305 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1);
309 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
313 for (i = 0; i < pdata->channel_count; i++) {
314 if (!pdata->channel[i]->rx_ring)
317 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1);
320 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
323 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
329 mutex_lock(&pdata->rss_mutex);
331 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
336 XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
338 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
339 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
340 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
341 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
345 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
354 mutex_unlock(&pdata->rss_mutex);
359 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
361 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
362 unsigned int *key = (unsigned int *)&pdata->rss_key;
366 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
375 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
380 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
381 ret = xgbe_write_rss_reg(pdata,
383 pdata->rss_table[i]);
391 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key)
393 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
395 return xgbe_write_rss_hash_key(pdata);
398 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata,
403 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
404 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
406 return xgbe_write_rss_lookup_table(pdata);
409 static int xgbe_enable_rss(struct xgbe_prv_data *pdata)
413 if (!pdata->hw_feat.rss)
417 ret = xgbe_write_rss_hash_key(pdata);
422 ret = xgbe_write_rss_lookup_table(pdata);
427 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
430 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
435 static int xgbe_disable_rss(struct xgbe_prv_data *pdata)
437 if (!pdata->hw_feat.rss)
440 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
445 static void xgbe_config_rss(struct xgbe_prv_data *pdata)
449 if (!pdata->hw_feat.rss)
452 if (pdata->netdev->features & NETIF_F_RXHASH)
453 ret = xgbe_enable_rss(pdata);
455 ret = xgbe_disable_rss(pdata);
458 netdev_err(pdata->netdev,
462 static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata,
469 if (pdata->prio2q_map[prio] != queue)
473 tc = pdata->ets->prio_tc[prio];
476 if (pdata->pfc->pfc_en & (1 << tc))
483 static void xgbe_set_vxlan_id(struct xgbe_prv_data *pdata)
486 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port);
488 netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n",
489 pdata->vxlan_port);
492 static void xgbe_enable_vxlan(struct xgbe_prv_data *pdata)
494 if (!pdata->hw_feat.vxn)
498 xgbe_set_vxlan_id(pdata);
501 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 1);
504 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNM, 0);
505 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 1);
507 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n");
510 static void xgbe_disable_vxlan(struct xgbe_prv_data *pdata)
512 if (!pdata->hw_feat.vxn)
516 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 0);
519 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 0);
522 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, 0);
524 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n");
527 static unsigned int xgbe_get_fc_queue_count(struct xgbe_prv_data *pdata)
532 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30)
535 return min_t(unsigned int, pdata->tx_q_count, max_q_count);
538 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
544 for (i = 0; i < pdata->rx_q_count; i++)
545 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
548 q_count = xgbe_get_fc_queue_count(pdata);
551 reg_val = XGMAC_IOREAD(pdata, reg);
553 XGMAC_IOWRITE(pdata, reg, reg_val);
561 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
563 struct ieee_pfc *pfc = pdata->pfc;
564 struct ieee_ets *ets = pdata->ets;
569 for (i = 0; i < pdata->rx_q_count; i++) {
572 if (pdata->rx_rfd[i]) {
575 if (xgbe_is_pfc_queue(pdata, i))
582 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc);
584 netif_dbg(pdata, drv, pdata->netdev,
590 q_count = xgbe_get_fc_queue_count(pdata);
593 reg_val = XGMAC_IOREAD(pdata, reg);
600 XGMAC_IOWRITE(pdata, reg, reg_val);
608 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
610 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
615 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
617 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
622 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
624 struct ieee_pfc *pfc = pdata->pfc;
626 if (pdata->tx_pause || (pfc && pfc->pfc_en))
627 xgbe_enable_tx_flow_control(pdata);
629 xgbe_disable_tx_flow_control(pdata);
634 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
636 struct ieee_pfc *pfc = pdata->pfc;
638 if (pdata->rx_pause || (pfc && pfc->pfc_en))
639 xgbe_enable_rx_flow_control(pdata);
641 xgbe_disable_rx_flow_control(pdata);
646 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
648 struct ieee_pfc *pfc = pdata->pfc;
650 xgbe_config_tx_flow_control(pdata);
651 xgbe_config_rx_flow_control(pdata);
653 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
657 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
663 if (pdata->channel_irq_mode)
664 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM,
665 pdata->channel_irq_mode);
667 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
669 for (i = 0; i < pdata->channel_count; i++) {
670 channel = pdata->channel[i];
699 if (!pdata->per_channel_irq || pdata->channel_irq_mode)
711 if (!pdata->per_channel_irq || pdata->channel_irq_mode)
720 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
725 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
728 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
729 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
732 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
736 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
743 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
746 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
747 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
750 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1);
753 static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata)
757 if (!pdata->vdata->ecc_support)
761 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
762 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
772 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
775 static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata)
779 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
786 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
789 static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata,
794 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
809 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
812 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed)
830 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss)
831 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss);
836 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
839 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
842 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
845 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
848 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
851 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
856 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
858 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
863 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
866 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
869 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
872 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
875 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
883 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
888 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
891 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
920 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
928 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
937 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
942 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
947 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
950 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n",
952 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
956 xgbe_disable_rx_vlan_filtering(pdata);
958 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
959 xgbe_enable_rx_vlan_filtering(pdata);
965 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
970 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
973 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n",
975 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
980 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
999 netif_dbg(pdata, drv, pdata->netdev,
1006 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
1008 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
1012 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
1014 struct net_device *netdev = pdata->netdev;
1020 addn_macs = pdata->hw_feat.addn_mac;
1023 xgbe_set_promiscuous_mode(pdata, 1);
1026 xgbe_set_mac_reg(pdata, ha, &mac_reg);
1031 xgbe_set_all_multicast_mode(pdata, 1);
1034 xgbe_set_mac_reg(pdata, ha, &mac_reg);
1042 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
1045 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
1047 struct net_device *netdev = pdata->netdev;
1055 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
1056 hash_table_count = pdata->hw_feat.hash_table_size / 32;
1075 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
1080 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
1082 if (pdata->hw_feat.hash_table_size)
1083 xgbe_set_mac_hash_table(pdata);
1085 xgbe_set_mac_addn_addrs(pdata);
1090 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
1098 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
1099 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
1104 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata)
1106 struct net_device *netdev = pdata->netdev;
1112 xgbe_set_promiscuous_mode(pdata, pr_mode);
1113 xgbe_set_all_multicast_mode(pdata, am_mode);
1115 xgbe_add_mac_addresses(pdata);
1120 static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
1127 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
1130 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
1135 static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
1142 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
1145 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
1150 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
1160 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1172 index = mmd_address & ~pdata->xpcs_window_mask;
1173 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
1175 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1176 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
1177 mmd_data = XPCS16_IOREAD(pdata, offset);
1178 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1183 static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
1192 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1204 index = mmd_address & ~pdata->xpcs_window_mask;
1205 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
1207 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1208 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
1209 XPCS16_IOWRITE(pdata, offset, mmd_data);
1210 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1213 static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad,
1223 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1234 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1235 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
1236 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2);
1237 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1242 static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad,
1251 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1262 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1263 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
1264 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
1265 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1268 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
1271 switch (pdata->vdata->xpcs_access) {
1273 return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg);
1277 return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg);
1281 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
1284 switch (pdata->vdata->xpcs_access) {
1286 return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data);
1290 return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data);
1308 static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr,
1313 reinit_completion(&pdata->mdio_complete);
1316 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
1322 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
1324 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) {
1325 netdev_err(pdata->netdev, "mdio write operation timed out\n");
1332 static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr,
1337 reinit_completion(&pdata->mdio_complete);
1340 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
1345 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
1347 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) {
1348 netdev_err(pdata->netdev, "mdio read operation timed out\n");
1352 return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA);
1355 static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port,
1358 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R);
1372 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val);
1382 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
1384 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
1389 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
1391 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
1445 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata,
1449 unsigned int rx_usecs = pdata->rx_usecs;
1450 unsigned int rx_frames = pdata->rx_frames;
1495 struct xgbe_prv_data *pdata = channel->pdata;
1508 xgbe_rx_desc_reset(pdata, rdata, i);
1529 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1535 XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1536 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1539 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1543 netdev_err(pdata->netdev,
1547 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1553 XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1554 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1555 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1558 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1562 netdev_err(pdata->netdev, "timed out initializing timestamp\n");
1565 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1569 nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1571 nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1576 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1581 if (pdata->vdata->tx_tstamp_workaround) {
1582 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1583 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
1585 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
1586 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1617 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1629 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1636 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1637 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1638 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1639 xgbe_set_tstamp_time(pdata, 0, 0);
1642 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1651 struct xgbe_prv_data *pdata = channel->pdata;
1664 if (pdata->tx_usecs && !channel->tx_timer_active) {
1667 jiffies + usecs_to_jiffies(pdata->tx_usecs));
1675 struct xgbe_prv_data *pdata = channel->pdata;
1723 if (!pdata->tx_frames)
1725 else if (tx_packets > pdata->tx_frames)
1727 else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets)
1738 netif_dbg(pdata, tx_queued, pdata->netdev,
1758 netif_dbg(pdata, tx_queued, pdata->netdev,
1817 pdata->ext_stats.tx_tso_packets += tx_packets;
1836 pdata->ext_stats.tx_vxlan_packets += packet->tx_packets;
1875 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets;
1876 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes;
1889 if (netif_msg_tx_queued(pdata))
1890 xgbe_dump_tx_desc(pdata, ring, start_index,
1898 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
1913 struct xgbe_prv_data *pdata = channel->pdata;
1918 struct net_device *netdev = pdata->netdev;
1933 if (netif_msg_rx_status(pdata))
1934 xgbe_dump_rx_desc(pdata, ring, ring->cur);
1962 pdata->ext_stats.rx_split_header_packets++;
2011 pdata->ext_stats.rx_vxlan_packets++;
2026 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt);
2037 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n",
2049 pdata->ext_stats.rx_csum_errors++;
2055 pdata->ext_stats.rx_vxlan_csum_errors++;
2062 pdata->ext_stats.rxq_packets[channel->queue_index]++;
2063 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len;
2166 static int __xgbe_exit(struct xgbe_prv_data *pdata)
2173 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
2177 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
2188 static int xgbe_exit(struct xgbe_prv_data *pdata)
2195 ret = __xgbe_exit(pdata);
2199 return __xgbe_exit(pdata);
2202 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
2206 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
2209 for (i = 0; i < pdata->tx_q_count; i++)
2210 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
2213 for (i = 0; i < pdata->tx_q_count; i++) {
2215 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i,
2226 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
2230 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR);
2237 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2);
2238 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal);
2239 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1);
2240 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1);
2242 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr);
2245 if (pdata->vdata->tx_desc_prefetch)
2246 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS,
2247 pdata->vdata->tx_desc_prefetch);
2249 if (pdata->vdata->rx_desc_prefetch)
2250 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS,
2251 pdata->vdata->rx_desc_prefetch);
2254 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
2256 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr);
2257 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr);
2258 if (pdata->awarcr)
2259 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr);
2262 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
2267 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
2270 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
2271 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2273 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
2277 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
2280 static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata,
2287 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata));
2289 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) {
2291 rfa = pdata->pfc_rfa;
2305 pdata->rx_rfa[queue] = 0;
2306 pdata->rx_rfd[queue] = 0;
2312 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */
2313 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */
2319 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */
2320 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */
2341 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa);
2342 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd);
2345 static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata,
2351 for (i = 0; i < pdata->rx_q_count; i++) {
2354 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size);
2358 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
2362 for (i = 0; i < pdata->rx_q_count; i++) {
2363 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA,
2364 pdata->rx_rfa[i]);
2365 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD,
2366 pdata->rx_rfd[i]);
2370 static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata)
2373 return min_t(unsigned int, pdata->tx_max_fifo_size,
2374 pdata->hw_feat.tx_fifo_size);
2377 static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata)
2380 return min_t(unsigned int, pdata->rx_max_fifo_size,
2381 pdata->hw_feat.rx_fifo_size);
2430 static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata)
2435 if (pdata->pfc->delay)
2436 return pdata->pfc->delay / 8;
2439 delay = xgbe_get_max_frame(pdata);
2454 static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata)
2459 if (!pdata->pfc->pfc_en)
2463 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2465 if (!xgbe_is_pfc_queue(pdata, i))
2468 pdata->pfcq[i] = 1;
2475 static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata,
2484 q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata));
2485 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2486 pfc_count = xgbe_get_pfc_queues(pdata);
2500 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata);
2501 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa);
2503 if (pdata->pfc_rfa > q_fifo_size) {
2504 addn_fifo = pdata->pfc_rfa - q_fifo_size;
2521 if (!pdata->pfcq[i] || !addn_fifo)
2525 netdev_warn(pdata->netdev,
2546 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
2552 fifo_size = xgbe_get_tx_fifo_size(pdata);
2554 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo);
2556 for (i = 0; i < pdata->tx_q_count; i++)
2557 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]);
2559 netif_info(pdata, drv, pdata->netdev,
2561 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
2564 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
2572 memset(pdata->pfcq, 0, sizeof(pdata->pfcq));
2573 pdata->pfc_rfa = 0;
2575 fifo_size = xgbe_get_rx_fifo_size(pdata);
2576 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2579 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo);
2581 if (pdata->pfc && pdata->ets)
2582 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo);
2586 for (i = 0; i < pdata->rx_q_count; i++)
2587 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]);
2589 xgbe_calculate_flow_control_threshold(pdata, fifo);
2590 xgbe_config_flow_control_threshold(pdata);
2592 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) {
2593 netif_info(pdata, drv, pdata->netdev,
2594 "%u Rx hardware queues\n", pdata->rx_q_count);
2595 for (i = 0; i < pdata->rx_q_count; i++)
2596 netif_info(pdata, drv, pdata->netdev,
2600 netif_info(pdata, drv, pdata->netdev,
2602 pdata->rx_q_count,
2607 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
2618 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
2619 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
2621 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
2623 netif_dbg(pdata, drv, pdata->netdev,
2625 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2627 pdata->q2tc_map[queue++] = i;
2631 netif_dbg(pdata, drv, pdata->netdev,
2633 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2635 pdata->q2tc_map[queue++] = i;
2640 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2649 netif_dbg(pdata, drv, pdata->netdev,
2652 pdata->prio2q_map[prio++] = i;
2656 netif_dbg(pdata, drv, pdata->netdev,
2659 pdata->prio2q_map[prio++] = i;
2667 XGMAC_IOWRITE(pdata, reg, reg_val);
2675 for (i = 0; i < pdata->rx_q_count;) {
2678 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
2681 XGMAC_IOWRITE(pdata, reg, reg_val);
2688 static void xgbe_config_tc(struct xgbe_prv_data *pdata)
2693 netdev_reset_tc(pdata->netdev);
2694 if (!pdata->num_tcs)
2697 netdev_set_num_tc(pdata->netdev, pdata->num_tcs);
2699 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) {
2700 while ((queue < pdata->tx_q_count) &&
2701 (pdata->q2tc_map[queue] == i))
2704 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n",
2706 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset);
2710 if (!pdata->ets)
2714 netdev_set_prio_tc_map(pdata->netdev, prio,
2715 pdata->ets->prio_tc[prio]);
2718 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
2720 struct ieee_ets *ets = pdata->ets;
2731 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
2734 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
2739 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
2748 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n",
2751 reg_val = XGMAC_IOREAD(pdata, reg);
2756 XGMAC_IOWRITE(pdata, reg, reg_val);
2761 netif_dbg(pdata, drv, pdata->netdev,
2763 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2770 netif_dbg(pdata, drv, pdata->netdev,
2772 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2774 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
2780 xgbe_config_tc(pdata);
2783 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
2785 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) {
2787 netif_tx_stop_all_queues(pdata->netdev);
2790 pdata->hw_if.disable_rx(pdata);
2793 xgbe_config_rx_fifo_size(pdata);
2794 xgbe_config_flow_control(pdata);
2796 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) {
2798 pdata->hw_if.enable_rx(pdata);
2801 netif_tx_start_all_queues(pdata->netdev);
2805 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
2807 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
2810 if (pdata->hw_feat.hash_table_size) {
2811 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
2812 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
2813 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
2817 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
2821 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
2823 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
2826 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
2828 xgbe_set_speed(pdata, pdata->phy_speed);
2831 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
2833 if (pdata->netdev->features & NETIF_F_RXCSUM)
2834 xgbe_enable_rx_csum(pdata);
2836 xgbe_disable_rx_csum(pdata);
2839 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
2842 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
2843 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
2846 xgbe_update_vlan_hash_table(pdata);
2848 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
2849 xgbe_enable_rx_vlan_filtering(pdata);
2851 xgbe_disable_rx_vlan_filtering(pdata);
2853 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2854 xgbe_enable_rx_vlan_stripping(pdata);
2856 xgbe_disable_rx_vlan_stripping(pdata);
2859 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
2864 if (pdata->vdata->mmc_64bit) {
2893 val = XGMAC_IOREAD(pdata, reg_lo);
2896 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
2901 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
2903 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2904 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
2908 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2912 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2916 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2920 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2924 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2928 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2932 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2936 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2940 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2944 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2948 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2952 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2956 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2960 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2964 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2968 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2972 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2976 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2979 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2981 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2982 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2986 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2990 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2994 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2998 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
3002 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
3006 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
3010 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
3014 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
3018 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
3022 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
3026 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
3030 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
3034 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
3038 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
3042 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
3046 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
3050 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
3054 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
3058 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
3062 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
3066 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
3070 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
3074 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
3077 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
3079 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
3082 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
3085 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
3088 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
3091 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
3094 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
3097 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
3100 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
3103 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
3106 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
3109 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
3112 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
3115 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
3118 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
3121 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
3124 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
3127 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
3130 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
3133 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
3136 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
3139 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
3142 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
3145 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
3148 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
3151 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
3154 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
3157 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
3160 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
3163 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
3166 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
3169 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
3172 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
3175 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
3178 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
3181 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
3184 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
3187 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
3190 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
3193 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
3196 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
3199 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
3202 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
3205 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
3208 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
3211 static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
3214 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
3217 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
3220 static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata,
3232 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
3241 netdev_info(pdata->netdev,
3246 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata,
3253 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20)
3254 return xgbe_txq_prepare_tx_stop(pdata, queue);
3274 tx_status = XGMAC_IOREAD(pdata, tx_dsr);
3284 netdev_info(pdata->netdev,
3289 static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
3294 for (i = 0; i < pdata->channel_count; i++) {
3295 if (!pdata->channel[i]->tx_ring)
3298 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
3302 for (i = 0; i < pdata->tx_q_count; i++)
3303 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
3307 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
3310 static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
3315 for (i = 0; i < pdata->tx_q_count; i++)
3316 xgbe_prepare_tx_stop(pdata, i);
3319 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
3322 for (i = 0; i < pdata->tx_q_count; i++)
3323 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
3326 for (i = 0; i < pdata->channel_count; i++) {
3327 if (!pdata->channel[i]->tx_ring)
3330 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
3334 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata,
3346 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
3355 netdev_info(pdata->netdev,
3360 static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
3365 for (i = 0; i < pdata->channel_count; i++) {
3366 if (!pdata->channel[i]->rx_ring)
3369 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
3374 for (i = 0; i < pdata->rx_q_count; i++)
3376 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
3379 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
3380 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
3381 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
3382 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
3385 static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
3390 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
3391 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
3392 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
3393 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
3396 for (i = 0; i < pdata->rx_q_count; i++)
3397 xgbe_prepare_rx_stop(pdata, i);
3400 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
3403 for (i = 0; i < pdata->channel_count; i++) {
3404 if (!pdata->channel[i]->rx_ring)
3407 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
3411 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
3416 for (i = 0; i < pdata->channel_count; i++) {
3417 if (!pdata->channel[i]->tx_ring)
3420 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
3424 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
3427 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
3432 for (i = 0; i < pdata->tx_q_count; i++)
3433 xgbe_prepare_tx_stop(pdata, i);
3436 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
3439 for (i = 0; i < pdata->channel_count; i++) {
3440 if (!pdata->channel[i]->tx_ring)
3443 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
3447 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
3452 for (i = 0; i < pdata->channel_count; i++) {
3453 if (!pdata->channel[i]->rx_ring)
3456 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
3460 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
3465 for (i = 0; i < pdata->channel_count; i++) {
3466 if (!pdata->channel[i]->rx_ring)
3469 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
3473 static int xgbe_init(struct xgbe_prv_data *pdata)
3475 struct xgbe_desc_if *desc_if = &pdata->desc_if;
3481 ret = xgbe_flush_tx_queues(pdata);
3483 netdev_err(pdata->netdev, "error flushing TX queues\n");
3490 xgbe_config_dma_bus(pdata);
3491 xgbe_config_dma_cache(pdata);
3492 xgbe_config_osp_mode(pdata);
3493 xgbe_config_pbl_val(pdata);
3494 xgbe_config_rx_coalesce(pdata);
3495 xgbe_config_tx_coalesce(pdata);
3496 xgbe_config_rx_buffer_size(pdata);
3497 xgbe_config_tso_mode(pdata);
3498 xgbe_config_sph_mode(pdata);
3499 xgbe_config_rss(pdata);
3500 desc_if->wrapper_tx_desc_init(pdata);
3501 desc_if->wrapper_rx_desc_init(pdata);
3502 xgbe_enable_dma_interrupts(pdata);
3507 xgbe_config_mtl_mode(pdata);
3508 xgbe_config_queue_mapping(pdata);
3509 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
3510 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
3511 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
3512 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
3513 xgbe_config_tx_fifo_size(pdata);
3514 xgbe_config_rx_fifo_size(pdata);
3518 xgbe_config_dcb_tc(pdata);
3519 xgbe_enable_mtl_interrupts(pdata);
3524 xgbe_config_mac_address(pdata);
3525 xgbe_config_rx_mode(pdata);
3526 xgbe_config_jumbo_enable(pdata);
3527 xgbe_config_flow_control(pdata);
3528 xgbe_config_mac_speed(pdata);
3529 xgbe_config_checksum_offload(pdata);
3530 xgbe_config_vlan_support(pdata);
3531 xgbe_config_mmc(pdata);
3532 xgbe_enable_mac_interrupts(pdata);
3537 xgbe_enable_ecc_interrupts(pdata);