Lines Matching defs:queue
463 unsigned int queue)
468 /* Does this queue handle the priority? */
469 if (pdata->prio2q_map[prio] != queue)
531 /* From MAC ver 30H the TFCR is per priority, instead of per queue */
2281 unsigned int queue,
2289 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) {
2290 /* PFC is active for this queue */
2305 pdata->rx_rfa[queue] = 0;
2306 pdata->rx_rfd[queue] = 0;
2312 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */
2313 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */
2319 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */
2320 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */
2341 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa);
2342 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd);
2394 /* Calculate the fifo setting by dividing the queue's fifo size
2560 "%d Tx hardware queues, %d byte fifo per queue\n",
2571 /* Clear any DCB related fifo/queue information */
2597 "RxQ%u, %u byte fifo queue\n", i,
2601 "%u Rx hardware queues, %u byte fifo per queue\n",
2609 unsigned int qptc, qptc_extra, queue;
2621 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
2624 "TXq%u mapped to TC%u\n", queue, i);
2625 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2627 pdata->q2tc_map[queue++] = i;
2632 "TXq%u mapped to TC%u\n", queue, i);
2633 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2635 pdata->q2tc_map[queue++] = i;
2672 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2690 unsigned int offset, queue, prio;
2699 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) {
2700 while ((queue < pdata->tx_q_count) &&
2701 (pdata->q2tc_map[queue] == i))
2702 queue++;
2705 i, offset, queue - 1);
2706 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset);
2707 offset = queue;
3221 unsigned int queue)
3227 * packets. Wait for the Tx queue to empty the Tx fifo. Don't
3232 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
3242 "timed out waiting for Tx queue %u to empty\n",
3243 queue);
3247 unsigned int queue)
3254 return xgbe_txq_prepare_tx_stop(pdata, queue);
3257 if (queue < DMA_DSRX_FIRST_QUEUE) {
3259 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START;
3261 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE;
3286 queue);
3301 /* Enable each Tx queue */
3321 /* Disable each Tx queue */
3335 unsigned int queue)
3341 * packets. Wait for the Rx queue to empty the Rx fifo. Don't
3346 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
3356 "timed out waiting for Rx queue %u to empty\n",
3357 queue);
3372 /* Enable each Rx queue */
3399 /* Disable each Rx queue */