Lines Matching defs:fifo

2346 						  unsigned int *fifo)
2352 q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT;
2372 /* The configured value may not be the actual amount of fifo RAM */
2379 /* The configured value may not be the actual amount of fifo RAM */
2386 unsigned int *fifo)
2394 /* Calculate the fifo setting by dividing the queue's fifo size
2395 * by the fifo allocation increment (with 0 representing the
2402 /* Distribute the fifo equally amongst the queues */
2404 fifo[i] = p_fifo;
2409 unsigned int *fifo)
2420 * don't require a large fifo
2423 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1;
2477 unsigned int *fifo)
2490 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
2494 /* Calculate how much fifo we have to play with */
2497 /* Calculate how much more than base fifo PFC needs, which also
2510 /* Calculate DCB fifo settings:
2511 * - distribute remaining fifo between the VLAN priority
2519 fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1;
2526 "RXq%u cannot set needed fifo size\n", i);
2533 fifo[i] += (addn_fifo / XGMAC_FIFO_UNIT);
2540 /* Distribute remaining fifo across queues */
2542 fifo[i] += (inc_fifo / XGMAC_FIFO_UNIT);
2549 unsigned int fifo[XGBE_MAX_QUEUES];
2554 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo);
2557 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]);
2560 "%d Tx hardware queues, %d byte fifo per queue\n",
2561 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
2567 unsigned int fifo[XGBE_MAX_QUEUES];
2571 /* Clear any DCB related fifo/queue information */
2578 /* Assign a minimum fifo to the non-VLAN priority queues */
2579 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo);
2582 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo);
2584 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
2587 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]);
2589 xgbe_calculate_flow_control_threshold(pdata, fifo);
2597 "RxQ%u, %u byte fifo queue\n", i,
2598 ((fifo[i] + 1) * XGMAC_FIFO_UNIT));
2601 "%u Rx hardware queues, %u byte fifo per queue\n",
2603 ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
2786 /* Just stop the Tx queues while Rx fifo is changed */
2789 /* Suspend Rx so that fifo's can be adjusted */
3227 * packets. Wait for the Tx queue to empty the Tx fifo. Don't
3341 * packets. Wait for the Rx queue to empty the Rx fifo. Don't