Lines Matching refs:REGA
165 #define REGA(a) (*( AREG = (a), &DREG ))
360 REGA(CSR0) = CSR0_STOP;
425 REGA(CSR0) = CSR0_STOP;
430 REGA(CSR0) = CSR0_INIT;
503 REGA(CSR1) = dvma_vtob(&(MEM->init));
504 REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16;
507 REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON;
509 REGA(CSR3) = CSR3_BSWP;
539 REGA(CSR3) = CSR3_BSWP;
561 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
591 REGA( CSR0 ) = CSR0_STOP;
593 REGA( CSR0 ) = CSR0_INIT | CSR0_STRT;
637 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT;
709 REGA(CSR0) = CSR0_STOP;
710 REGA(CSR3) = CSR3_BSWP;
712 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
747 REGA(CSR0) = CSR0_STOP;
748 REGA(CSR3) = CSR3_BSWP;
750 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
758 REGA(CSR0) = CSR0_INEA;
902 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
912 REGA( CSR8+i ) = multicast_table[i];
913 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
920 REGA( CSR3 ) = CSR3_BSWP;
923 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;