Lines Matching refs:PORT
112 #define PORT p->cmdr_addr
159 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);inw(PORT+L_ADDRREG); \
160 outw(val,PORT+L_DATAREG);inw(PORT+L_DATAREG);}
161 #define readreg(reg) (outw(reg,PORT+L_ADDRREG),inw(PORT+L_ADDRREG),\
162 inw(PORT+L_DATAREG))
164 #define writedatareg(val) {outw(val,PORT+L_DATAREG);inw(PORT+L_DATAREG);}
169 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);}
170 #define readreg(reg) (outw(reg,PORT+L_ADDRREG),inw(PORT+L_DATAREG))
278 outw(80,PORT+L_ADDRREG);
279 if(inw(PORT+L_ADDRREG) != 80)
283 outw(0,PORT+L_ADDRREG);
284 outw((short)isa0,PORT+L_BUSIF); /* write ISA 0: DMA_R : isa0 * 50ns */
285 outw(1,PORT+L_ADDRREG);
286 outw((short)isa1,PORT+L_BUSIF); /* write ISA 1: DMA_W : isa1 * 50ns */
288 outw(CSR0,PORT+L_ADDRREG); /* switch back to CSR0 */
326 outw(inw(PORT+L_RESET),PORT+L_RESET); /* that's the hard way */
460 outw(inw(PORT+L_RESET),PORT+L_RESET); /* first: reset the card */
469 outw(88,PORT+L_ADDRREG);
470 if(inw(PORT+L_ADDRREG) == 88) {
472 v = inw(PORT+L_DATAREG);
474 outw(89,PORT+L_ADDRREG);
475 v |= inw(PORT+L_DATAREG);
595 if(inw(PORT+L_DATAREG) & (CSR0_IDON | CSR0_MERR) )
804 outw(inw(PORT+L_RESET),PORT+L_RESET); /* first: reset the card */
855 if(inw(PORT+L_DATAREG) & CSR0_IDON) {
861 printk(KERN_ERR "%s: can't init lance, status: %04x\n",dev->name,(int) inw(PORT+L_DATAREG));
883 csr0 = inw(PORT+L_DATAREG);
1067 dev->name,(int) rmdstat,csr0,(int) inw(PORT+L_DATAREG) );