Lines Matching defs:writedatareg
164 #define writedatareg(val) {outw(val,PORT+L_DATAREG);inw(PORT+L_DATAREG);}
166 #define writedatareg(val) { writereg(val,CSR0); }
171 #define writedatareg(val) { writereg(val,CSR0); }
723 writedatareg(CSR0_STOP);
761 writedatareg(CSR0_STRT | csr0);
770 writedatareg(CSR0_TDMD | CSR0_INEA | csr0);
783 writedatareg(CSR0_STRT | csr0);
858 writedatareg(CSR0_CLRALL | CSR0_INEA | CSR0_STRT);
886 writedatareg( (csr0 & CSR0_CLRALL) ); /* ack interrupts, disable int. */
888 writedatareg( (csr0 & CSR0_CLRALL) | CSR0_INEA ); /* ack interrupts, interrupts enabled */
970 writedatareg(CSR0_INEA);
1200 writedatareg(CSR0_TDMD | CSR0_INEA); /* enable xmit & interrupt */