Lines Matching refs:mmio
101 void __iomem *mmio = lp->mmio;
105 reg_val = readl(mmio + PHY_ACCESS);
107 reg_val = readl( mmio + PHY_ACCESS );
110 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
112 reg_val = readl(mmio + PHY_ACCESS);
131 void __iomem *mmio = lp->mmio;
134 reg_val = readl(mmio + PHY_ACCESS);
136 reg_val = readl( mmio + PHY_ACCESS );
139 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
142 reg_val = readl(mmio + PHY_ACCESS);
369 void __iomem *mmio = lp->mmio;
383 writel(VAL0|STINTEN, mmio+INTEN0);
385 mmio+DLY_INT_A);
397 writel(VAL0|STINTEN,mmio+INTEN0);
399 mmio+DLY_INT_B);
403 writel(0,mmio+STVAL);
404 writel(STINTEN, mmio+INTEN0);
405 writel(0, mmio +DLY_INT_B);
406 writel(0, mmio+DLY_INT_A);
410 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */
411 writel(VAL0|STINTEN, mmio+INTEN0);
425 void __iomem *mmio = lp->mmio;
429 writel(RUN, mmio + CMD0);
435 writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
436 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
441 reg_val = readl(mmio + CTRL1);
443 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
448 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
450 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
453 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
454 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
456 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
457 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
460 writew((u32)DEFAULT_IPG,mmio+IPG);
461 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
464 writel((u32)VAL2|JUMBO, mmio + CMD3);
466 writel( REX_UFLO, mmio + CMD2);
468 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
470 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
471 writel((u32)JUMBO, mmio + CMD3);
475 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
477 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
481 writeb( dev->dev_addr[i], mmio + PADR + i );
490 writel(VAL2 | RDMD0, mmio + CMD0);
491 writel(VAL0 | INTREN | RUN, mmio + CMD0);
494 readl(mmio+CMD0);
503 void __iomem *mmio = lp->mmio;
507 writel(RUN, mmio + CMD0);
510 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
513 writel(0, mmio + RCV_RING_BASE_ADDR0);
516 writel(0, mmio + XMT_RING_BASE_ADDR0);
517 writel(0, mmio + XMT_RING_BASE_ADDR1);
518 writel(0, mmio + XMT_RING_BASE_ADDR2);
519 writel(0, mmio + XMT_RING_BASE_ADDR3);
522 writel(CMD0_CLEAR,mmio + CMD0);
525 writel(CMD2_CLEAR, mmio +CMD2);
528 writel(CMD7_CLEAR , mmio + CMD7);
531 writel(0x0, mmio + DLY_INT_A);
532 writel(0x0, mmio + DLY_INT_B);
535 writel(0x0, mmio + FLOW_CONTROL);
538 reg_val = readl(mmio + INT0);
539 writel(reg_val, mmio + INT0);
542 writel(0x0, mmio + STVAL);
545 writel( INTEN0_CLEAR, mmio + INTEN0);
548 writel(0x0 , mmio + LADRF);
551 writel( 0x80010,mmio + SRAM_SIZE);
554 writel(0x0, mmio + RCV_RING_LEN0);
557 writel(0x0, mmio + XMT_RING_LEN0);
558 writel(0x0, mmio + XMT_RING_LEN1);
559 writel(0x0, mmio + XMT_RING_LEN2);
560 writel(0x0, mmio + XMT_RING_LEN3);
563 writel(0x0, mmio + XMT_RING_LIMIT);
566 writew(MIB_CLEAR, mmio + MIB_ADDR);
569 amd8111e_writeq(*(u64 *)logic_filter, mmio + LADRF);
572 reg_val = readl(mmio + SRAM_SIZE);
575 writel( VAL2|JUMBO, mmio + CMD3);
577 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
580 writel(CTRL1_DEFAULT, mmio + CTRL1);
583 readl(mmio + CMD2);
595 writel(INTREN, lp->mmio + CMD0);
598 intr0 = readl(lp->mmio + INT0);
599 writel(intr0, lp->mmio + INT0);
602 readl(lp->mmio + INT0);
609 writel(RUN, lp->mmio + CMD0);
612 readl(lp->mmio + CMD0);
687 void __iomem *mmio = lp->mmio;
784 writel(VAL0|RINTEN0, mmio + INTEN0);
785 writel(VAL2 | RDMD0, mmio + CMD0);
799 status0 = readl(lp->mmio + STAT0);
837 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
843 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
845 status = readw(mmio + MIB_ADDR);
850 data = readl(mmio + MIB_DATA);
860 void __iomem *mmio = lp->mmio;
869 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
870 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
871 amd8111e_read_mib(mmio, rcv_unicast_pkts);
874 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
877 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
880 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
884 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
885 amd8111e_read_mib(mmio, rcv_fragments)+
886 amd8111e_read_mib(mmio, rcv_jabbers)+
887 amd8111e_read_mib(mmio, rcv_alignment_errors)+
888 amd8111e_read_mib(mmio, rcv_fcs_errors)+
889 amd8111e_read_mib(mmio, rcv_miss_pkts)+
893 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
896 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
899 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
902 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
905 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
909 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
910 amd8111e_read_mib(mmio, rcv_oversize_pkts);
913 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
916 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
920 amd8111e_read_mib(mmio, rcv_alignment_errors);
923 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
926 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
930 amd8111e_read_mib(mmio, xmt_excessive_collision);
934 amd8111e_read_mib(mmio, xmt_loss_carrier);
937 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
941 amd8111e_read_mib(mmio, xmt_late_collision);
944 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
1090 void __iomem *mmio = lp->mmio;
1100 writel(INTREN, mmio + CMD0);
1103 intr0 = readl(mmio + INT0);
1104 intren0 = readl(mmio + INTEN0);
1114 writel(intr0, mmio + INT0);
1120 writel(RINTEN0, mmio + INTEN0);
1126 writel(RINTEN0, mmio + INTEN0);
1143 writel( VAL0 | INTREN,mmio + CMD0);
1292 writel( VAL1 | TDMD0, lp->mmio + CMD0);
1293 writel( VAL2 | RDMD0,lp->mmio + CMD0);
1304 void __iomem *mmio = lp->mmio;
1306 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1307 buf[1] = readl(mmio + XMT_RING_LEN0);
1308 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1309 buf[3] = readl(mmio + RCV_RING_LEN0);
1310 buf[4] = readl(mmio + CMD0);
1311 buf[5] = readl(mmio + CMD2);
1312 buf[6] = readl(mmio + CMD3);
1313 buf[7] = readl(mmio + CMD7);
1314 buf[8] = readl(mmio + INT0);
1315 buf[9] = readl(mmio + INTEN0);
1316 buf[10] = readl(mmio + LADRF);
1317 buf[11] = readl(mmio + LADRF+4);
1318 buf[12] = readl(mmio + STAT0);
1333 writel( VAL2 | PROM, lp->mmio + CMD2);
1337 writel( PROM, lp->mmio + CMD2);
1343 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1350 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1352 writel(PROM, lp->mmio + CMD2);
1362 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1365 readl(lp->mmio + CMD2);
1514 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1540 writel(RUN, lp->mmio + CMD0);
1553 writel( VAL1|MPPLBA, lp->mmio + CMD3);
1554 writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1557 readl(lp->mmio + CMD7);
1565 writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1568 readl(lp->mmio + CMD7);
1655 void __iomem *mmio = lp->mmio;
1684 amd8111e_read_mib(mmio, xmt_collisions);
1703 writew((u32)tmp_ipg, mmio + IPG);
1704 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1811 lp->mmio = devm_ioremap(&pdev->dev, reg_addr, reg_len);
1812 if (!lp->mmio) {
1820 dev->dev_addr[i] = readb(lp->mmio + PADR + i);
1873 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;